163 lines
6.9 KiB
Python
Executable File
163 lines
6.9 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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from migen import *
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from litex_boards.platforms import arty
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from litex.soc.cores.clock import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litedram.common import PHYPadsReducer
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from litedram.phy import s7ddrphy
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from litedram.modules import MT41K128M16
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from liteeth.phy.mii import LiteEthPHYMII
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module, AutoCSR):
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def __init__(self, platform, sys_clk_freq):
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self.rst = Signal()
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self.clock_domains.cd_sys_pll = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_uart = ClockDomain()
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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# Main PLL.
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self.submodules.main_pll = main_pll = S7PLL(speedgrade=-1)
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self.comb += main_pll.reset.eq(~platform.request("cpu_reset"))
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main_pll.register_clkin(platform.request("clk100"), 100e6)
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main_pll.create_clkout(self.cd_sys_pll, sys_clk_freq)
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main_pll.create_clkout(self.cd_clk200, 200e6)
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main_pll.create_clkout(self.cd_uart, 100e6)
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main_pll.create_clkout(self.cd_eth, 25e6)
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main_pll.expose_drp()
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
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self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
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# DRAM PLL.
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~main_pll.locked | self.rst)
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pll.register_clkin(self.cd_sys_pll.clk, sys_clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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# Sys Clk Counter.
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self.sys_clk_counter = CSRStatus(32)
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self.sync += self.sys_clk_counter.status.eq(self.sys_clk_counter.status + 1)
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
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platform = arty.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
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ident = "LiteDRAM bench on Arty",
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integrated_rom_size = 0x10000,
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integrated_rom_mode = "rw",
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uart_name = uart)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# DDR3 SDRAM -------------------------------------------------------------------------------
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
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pads = PHYPadsReducer(platform.request("ddram"), [0, 1]),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41K128M16(sys_clk_freq, "1:4"),
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origin = self.mem_map["main_ram"],
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with_bist = with_bist)
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# UARTBone ---------------------------------------------------------------------------------
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if uart != "serial":
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self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"),
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with_hw_init_reset = False)
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self.add_etherbone(phy=self.ethphy)
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# Analyzer ---------------------------------------------------------------------------------
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if with_analyzer:
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from litescope import LiteScopeAnalyzer
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analyzer_signals = [self.ddrphy.dfi]
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self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
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depth = 256,
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clock_domain = "sys",
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csr_csv = "analyzer.csv")
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# Leds -------------------------------------------------------------------------------------
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from litex.soc.cores.led import LedChaser
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self.submodules.leds = LedChaser(
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pads = platform.request_all("user_led"),
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sys_clk_freq = sys_clk_freq)
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# Main ---------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteDRAM Bench on Arty A7")
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parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
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parser.add_argument("--with-analyzer", action="store_true", help="Add Analyzer")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
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parser.add_argument("--sys-clk-freq", default=None, help="Set sys_clk_freq")
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parser.add_argument("--test", action="store_true", help="Run Full Bench")
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args = parser.parse_args()
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soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
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builder = Builder(soc, output_dir="build/arty", csr_csv="csr.csv")
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builder.build(run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if args.load_bios:
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from common import load_bios
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load_bios("build/arty/software/bios/bios.bin")
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if args.sys_clk_freq is not None:
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from common import s7_set_sys_clk
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s7_set_sys_clk(clk_freq=float(args.sys_clk_freq), vco_freq=soc.crg.main_pll.compute_config()["vco"])
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if args.test:
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from common import s7_bench_test
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s7_bench_test(
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freq_min = 60e6,
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freq_max = 150e6,
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freq_step = 1e6,
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vco_freq = soc.crg.main_pll.compute_config()["vco"],
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bios_filename = "build/arty/software/bios/bios.bin")
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if __name__ == "__main__":
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main()
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