Florent Kermarrec 3f84cc9116 ddr3_mr_gen: Also display RZQ/x on configured electrical settings.		2022-02-24 16:33:46 +01:00
..
arty.py	bench/test: Avoid use of ident_version (should fix CI).	2022-02-15 17:33:31 +01:00
common.py	bench/common/bench_test: Improve UART dump speed.	2021-06-29 12:38:44 +02:00
ddr3_mr_gen.py	ddr3_mr_gen: Also display RZQ/x on configured electrical settings.	2022-02-24 16:33:46 +01:00
ddr4_mr_gen.py	bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).	2020-11-06 14:44:36 +01:00
genesys2.py	bench/test: Avoid use of ident_version (should fix CI).	2022-02-15 17:33:31 +01:00
kc705.py	bench/test: Avoid use of ident_version (should fix CI).	2022-02-15 17:33:31 +01:00
kcu105.py	bench/test: Avoid use of ident_version (should fix CI).	2022-02-15 17:33:31 +01:00
xcu1525.py	bench/test: Avoid use of ident_version (should fix CI).	2022-02-15 17:33:31 +01:00