Florent Kermarrec e5e4f528d4 examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright		2020-01-27 18:30:24 +01:00
..
arty.yml	litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY)	2020-01-27 18:20:16 +01:00
genesys2.yml	litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY)	2020-01-27 18:20:16 +01:00
nexys4ddr.yml	litedram_gen: cleanup SDRAM PHY selection, remove plarform configuration parameter (can be deduced from PHY)	2020-01-27 18:20:16 +01:00
versa_ecp5.yml	examples/versa_ecp5.yml: enable CPU (required for DDR3 calibration), update copyright	2020-01-27 18:30:24 +01:00