Florent Kermarrec 596615a238 bench/common: add progress to load_rom.		2020-12-10 19:22:46 +01:00
..
arty.py	bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.	2020-12-10 19:06:19 +01:00
common.py	bench/common: add progress to load_rom.	2020-12-10 19:22:46 +01:00
ddr3_mr_gen.py	bench: add DDR3 Mode Register settings generator.	2020-09-24 17:51:22 +02:00
ddr4_mr_gen.py	bench/ddr4_mr_gen.py: change default cl to 9 (cl value for sys_clk_freq=125e6).	2020-11-06 14:44:36 +01:00
genesys2.py	bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.	2020-12-10 19:06:19 +01:00
kc705.py	bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.	2020-12-10 19:06:19 +01:00
kcu105.py	bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.	2020-12-10 19:06:19 +01:00
xcu1525.py	bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.	2020-12-10 19:06:19 +01:00