litedram/litedram
enjoy-digital 16eb5a931c
Merge pull request #351 from trabucayre/gw5a_ddr3
phy/gw5ddrphy: introducing GW5A DDR phy
2023-11-09 11:43:26 +01:00
..
core core/bankmachine: Switch back to Replicate since Constant does not support 0-width. 2023-07-07 12:38:56 +02:00
frontend frontend/dma/LiteDRAMDMAReader: Simplify FIFO reservation and add last generation support. 2023-07-11 16:40:52 +02:00
phy phy/gw5ddrphy: introducing GW5A DDR phy 2023-11-09 11:42:48 +01:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py Add support for clam shell topology (#332) 2023-05-25 22:20:21 +02:00
dfii.py Add support for clam shell topology (#332) 2023-05-25 22:20:21 +02:00
gen.py Avalon frontend for LiteDRAM (#337) 2023-05-23 14:52:05 +02:00
init.py litedram/init: Cleanup supported memory generation. 2023-08-29 16:42:42 +02:00
modules.py add W9812G6JB SDRAM module 2023-11-09 10:28:39 +07:00