Florent Kermarrec 8d24163a86 phy/s7ddrphy: use our own bitslip module in fabric ... we could probably reduce added latency to 2 or 1 in the future.		2018-10-18 13:40:58 +02:00
..
core	core/bankmachine: manage tRC	2018-10-15 08:34:41 +02:00
frontend	ecc: update core/test	2018-10-12 17:13:53 +02:00
phy	phy/s7ddrphy: use our own bitslip module in fabric	2018-10-18 13:40:58 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	remove partial reordering code in master, keep things in bank_reordering branch.	2018-10-11 19:40:31 +02:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules: update K4B2G1646F and use timings from datasheet	2018-10-15 08:51:08 +02:00
sdram_init.py	sdram_init: min value for wr is 5	2018-09-05 23:40:04 +02:00