Florent Kermarrec 8e2df17747 modules: fix tRFC change on MT16KTF1G64HZ		2019-05-28 22:42:45 +02:00
..
core	core/crossbar: cosmetic	2019-01-22 13:56:35 +01:00
frontend	frontend/axi: move AXIBurst2Beat to LiteX	2019-04-19 12:14:13 +02:00
phy	PhySettings: add databits to allow SoC to compute memory size more easily	2019-05-10 15:44:44 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	PhySettings: add databits to allow SoC to compute memory size more easily	2019-05-10 15:44:44 +02:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	modules: fix tRFC change on MT16KTF1G64HZ	2019-05-28 22:42:45 +02:00
sdram_init.py	sdram_init: use "unsigned long" for address values	2019-04-29 15:00:13 -04:00