Florent Kermarrec a8c3d394ec sdram_init: fix compilation		2018-11-05 10:46:47 +01:00
..
core	core/bankmachine: typo	2018-10-19 18:20:12 +02:00
frontend	frontend/ecc: fix typo	2018-11-04 17:07:00 +01:00
phy	phy/kusddrphy: more genericity, initial DDR4 support	2018-11-05 10:46:18 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common: add DDR4 burst_length	2018-11-05 10:46:34 +01:00
dfii.py	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
modules.py	sdram_init: add initial DDR4 initialization	2018-11-05 09:32:08 +01:00
sdram_init.py	sdram_init: fix compilation	2018-11-05 10:46:47 +01:00