133 lines
3.3 KiB
Python
133 lines
3.3 KiB
Python
from litex.gen import *
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from litex.soc.interconnect import stream
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class PhySettings:
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def __init__(self, memtype, dfi_databits,
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nphases,
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rdphase, wrphase,
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rdcmdphase, wrcmdphase,
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cl, read_latency, write_latency, cwl=0):
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self.memtype = memtype
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self.dfi_databits = dfi_databits
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self.nphases = nphases
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self.rdphase = rdphase
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self.wrphase = wrphase
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self.rdcmdphase = rdcmdphase
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self.wrcmdphase = wrcmdphase
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self.cl = cl
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self.read_latency = read_latency
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self.write_latency = write_latency
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self.cwl = cwl
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class GeomSettings:
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def __init__(self, bankbits, rowbits, colbits):
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self.bankbits = bankbits
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self.rowbits = rowbits
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self.colbits = colbits
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self.addressbits = max(rowbits, colbits)
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class TimingSettings:
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def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC):
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self.tRP = tRP
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self.tRCD = tRCD
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self.tWR = tWR
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self.tWTR = tWTR
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self.tREFI = tREFI
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self.tRFC = tRFC
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def cmd_layout(aw):
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return [
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("valid", 1, DIR_M_TO_S),
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("ready", 1, DIR_S_TO_M),
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("we", 1, DIR_M_TO_S),
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("adr", aw, DIR_M_TO_S),
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("lock", 1, DIR_S_TO_M), # only used internally
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("wdata_ready", 1, DIR_S_TO_M),
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("rdata_valid", 1, DIR_S_TO_M)
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]
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def data_layout(dw):
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return [
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("wdata", dw, DIR_M_TO_S),
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("wdata_we", dw//8, DIR_M_TO_S),
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("rdata", dw, DIR_S_TO_M)
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]
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class LiteDRAMInterface(Record):
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def __init__(self, address_align, settings):
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self.aw = settings.geom.rowbits + settings.geom.colbits - address_align
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self.dw = settings.phy.dfi_databits*settings.phy.nphases
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self.nbanks = 2**settings.geom.bankbits
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self.settings = settings
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layout = [("bank"+str(i), cmd_layout(self.aw)) for i in range(self.nbanks)]
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layout += data_layout(self.dw)
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Record.__init__(self, layout)
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def cmd_description(aw):
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return [
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("we", 1),
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("adr", aw)
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]
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def wdata_description(dw):
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return [
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("data", dw),
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("we", dw//8)
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]
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def rdata_description(dw):
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return [("data", dw)]
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class LiteDRAMPort:
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def __init__(self, mode, aw, dw, cd="sys"):
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self.mode = mode
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self.aw = aw
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self.dw = dw
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self.cd = cd
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self.lock = Signal()
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self.cmd = stream.Endpoint(cmd_description(aw))
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self.wdata = stream.Endpoint(wdata_description(dw))
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self.rdata = stream.Endpoint(rdata_description(dw))
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self.flush = Signal()
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class LiteDRAMWritePort(LiteDRAMPort):
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def __init__(self, *args, **kwargs):
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LiteDRAMPort.__init__(self, "write", *args, **kwargs)
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class LiteDRAMReadPort(LiteDRAMPort):
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def __init__(self, *args, **kwargs):
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LiteDRAMPort.__init__(self, "read", *args, **kwargs)
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def cmd_request_layout(a, ba):
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return [
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("a", a),
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("ba", ba),
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("cas", 1),
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("ras", 1),
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("we", 1)
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]
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def cmd_request_rw_layout(a, ba):
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return cmd_request_layout(a, ba) + [
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("is_cmd", 1),
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("is_read", 1),
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("is_write", 1)
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]
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