Florent Kermarrec ac43e0118e phy/x7ddrphy: ease understanding of read latency loop range		2017-02-10 12:57:08 +01:00
..
core	core: fix refresh (bug was reducing controller throughput by 2)	2016-06-13 13:11:41 +02:00
frontend	frontend/bist: rename err_count to errors	2017-01-17 14:30:23 +01:00
phy	phy/x7ddrphy: ease understanding of read latency loop range	2017-02-10 12:57:08 +01:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter	2016-12-15 19:07:43 +01:00
dfii.py	only use positive logic in the controller(cas/ras/we) and use Record/stream.Endpoint for command requests	2016-05-02 12:18:56 +02:00
modules.py	move SDRAM modules in modules.py and others settings in common.py	2016-04-29 19:08:56 +02:00