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litedram/test
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Florent Kermarrec 095180be6a frontend/AXI: Add optional Read-Modify-Write mode for cases where w.strb is not available on the DRAM side (ex when ECC is enabled). 
When enabled, partial writes are automatically detected and a Read-Modify-Write access is
done. Before doing a RMW access, pending accesses are terminated and incoming accesses are
stalled until RMW access is done.

Enable with_read_modify_write in test_axi.
 		2022-02-28 18:45:46 +01:00
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primitives
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reference
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spd_data
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summary test: fix wrong sorting in benchmarks summary 2020-02-20 09:20:38 +01:00
__init__.py
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access_pattern.csv
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benchmark.py test/benchmark: Switch from soc_sdram (deprecated) to soc_core. 2022-01-07 18:37:13 +01:00
benchmarks.yml test: update benchmark configuration generator 2020-02-12 15:42:50 +01:00
common.py test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00
gen_access_pattern.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
gen_config.py
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phy_common.py phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
run_benchmarks.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_adaptation.py
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test_adapter.py
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test_axi.py
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test_bandwidth.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_bankmachine.py
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test_bist.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_command_chooser.py
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test_crossbar.py
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test_dfi.py phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
test_dma.py
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test_ecc.py
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test_examples.py litedram_gen: Add initial SDRAM support (with ULX3S example). 2021-07-02 09:01:31 +02:00
test_fifo.py
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test_init.py
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test_lpddr4.py
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test_lpddr5.py lpddr5: tests: add additional initial tCK delay for bitslip 2021-10-26 12:22:30 +02:00
test_modules.py
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test_multiplexer.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_phy_utils.py test/phy_common: simplify calls to run_simulation 2021-06-22 11:41:44 +02:00
test_refresh.py test/test_refresh: Update. 2021-11-01 15:33:21 +01:00
test_sim_utils.py phy/sim_utils: support low wait times (0/1) in PulseTiming 2021-10-26 12:22:30 +02:00
test_steerer.py
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test_timing.py
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test_wishbone.py test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00