712 lines
31 KiB
Python
712 lines
31 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import re
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import copy
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import unittest
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from typing import Mapping
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from functools import partial
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from collections import defaultdict
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from migen import *
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from litedram.phy.lpddr4.simphy import LPDDR4SimPHY, DoubleRateLPDDR4SimPHY
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from litedram.phy.lpddr4 import simsoc
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import test.phy_common
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from test.phy_common import DFISequencer, PadChecker
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# Migen simulator supports reset signals so we could add CRG to start all the signals
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# in the same time, however the clock signals will still be visible in the VCD dump
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# and the generators we assign to them will still work before reset. For this reason we
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# use clocks set up in such a way that we have all the phase aligned clocks start in tick
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# 1 (not zero), so that we avoid any issues with clock alignment.
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#
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# NOTE: On hardware proper reset must be ensured!
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#
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# The simulation should start like this:
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# sys |_--------------
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# sys_11_25 |___------------
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# sys8x |_----____----__
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# sys8x_ddr |_--__--__--__--
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# sys8x_90 |___----____----
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# sys8x_90_ddr |-__--__--__--__
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#
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# sys8x_90_ddr does not trigger at the simulation start (not an edge),
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# BUT a generator starts before first edge, so a `yield` is needed to wait until the first
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# rising edge!
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run_simulation = partial(test.phy_common.run_simulation, clocks={
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"sys": (64, 31),
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"sys2x": (32, 15),
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"sys8x": ( 8, 3),
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"sys8x_ddr": ( 4, 1),
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"sys8x_90": ( 8, 1),
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"sys8x_90_ddr": ( 4, 3),
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})
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dfi_data_to_dq = partial(test.phy_common.dfi_data_to_dq, databits=16, nphases=8, burst=16)
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dq_pattern = partial(test.phy_common.dq_pattern, databits=16, nphases=8, burst=16)
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class LPDDR4Tests(unittest.TestCase):
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SYS_CLK_FREQ = 100e6
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CMD_LATENCY = 2
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def run_test(self, dut, dfi_sequence, pad_checkers: Mapping[str, Mapping[str, str]], pad_generators=None, **kwargs):
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# pad_checkers: {clock: {sig: values}}
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dfi = DFISequencer(dfi_sequence)
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checkers = {clk: PadChecker(dut.pads, pad_signals) for clk, pad_signals in pad_checkers.items()}
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generators = defaultdict(list)
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generators["sys"].append(dfi.generator(dut.dfi))
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generators["sys"].append(dfi.reader(dut.dfi))
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for clock, checker in checkers.items():
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generators[clock].append(checker.run())
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pad_generators = pad_generators or {}
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for clock, gens in pad_generators.items():
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gens = gens if isinstance(gens, list) else [gens]
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for gen in gens:
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generators[clock].append(gen(dut.pads))
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run_simulation(dut, generators, **kwargs)
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PadChecker.assert_ok(self, checkers)
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dfi.assert_ok(self)
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def test_lpddr4_cs_phase_0(self):
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# Test that CS is serialized correctly when sending command on phase 0
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latency = '00000000' * self.CMD_LATENCY
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = [
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)}, # p0: READ
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],
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pad_checkers = {"sys8x_90": {
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'cs': latency + '10100000',
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}},
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)
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def test_lpddr4_clk(self):
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# Test clock serialization, first few cycles are undefined so ignore them
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latency = 'xxxxxxxx' * self.CMD_LATENCY
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = [
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{3: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)},
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],
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pad_checkers = {"sys8x_90_ddr": {
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'clk': latency + '01010101' * 3,
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}},
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)
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def test_lpddr4_cs_multiple_phases(self):
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# Test that CS is serialized on different phases and that overlapping commands are handled
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latency = '00000000' * self.CMD_LATENCY
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = [
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)},
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{3: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)},
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{
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1: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1),
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4: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1), # should be ignored
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},
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{
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1: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1),
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5: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1), # should NOT be ignored
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},
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{6: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)}, # crosses cycle boundaries
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)}, # should be ignored
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{2: dict(cs_n=1, cas_n=0, ras_n=1, we_n=1)}, # ignored due to cs_n=1
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],
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pad_checkers = {"sys8x_90": {
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'cs': latency + ''.join([
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'10100000', # p0
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'00010100', # p3
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'01010000', # p1, p4 ignored
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'01010101', # p1, p5
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'00000010', # p6 (cyc 0)
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'10000000', # p6 (cyc 1), p0 ignored
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'00000000', # p2 ignored
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])
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}},
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)
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def test_lpddr4_ca_sequencing(self):
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# Test proper serialization of commands to CA pads and that overlapping commands are handled
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latency = '00000000' * self.CMD_LATENCY
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read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = [
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{0: read, 3: read}, # p3 should be ignored
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{0: read, 4: read},
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{6: read},
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{0: read}, # ignored
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{7: read},
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{3: read}, # not ignored
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],
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pad_checkers = {"sys8x_90": {
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'cs': latency + '10100000' + '10101010' + '00000010' + '10000000' + '00000001' + '01010100',
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'ca0': latency + '00000000' + '00000000' + '00000000' + '00000000' + '00000000' + '00000000',
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'ca1': latency + '10100000' + '10101010' + '00000010' + '10000000' + '00000001' + '01010100',
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'ca2': latency + '00000000' + '00000000' + '00000000' + '00000000' + '00000000' + '00000000',
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'ca3': latency + '0x000000' + '0x000x00' + '0000000x' + '00000000' + '00000000' + 'x000x000',
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'ca4': latency + '00100000' + '00100010' + '00000000' + '10000000' + '00000000' + '01000100',
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'ca5': latency + '00000000' + '00000000' + '00000000' + '00000000' + '00000000' + '00000000',
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}},
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)
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def test_lpddr4_ca_addressing(self):
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# Test that bank/address for different commands are correctly serialized to CA pads
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latency = '00000000' * self.CMD_LATENCY
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read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, bank=0b101, address=0b1100110011) # actually invalid because CA[1:0] should always be 0
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write_ap = dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, bank=0b111, address=0b10000000000)
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activate = dict(cs_n=0, cas_n=1, ras_n=0, we_n=1, bank=0b010, address=0b11110000111100001)
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refresh_ab = dict(cs_n=0, cas_n=0, ras_n=0, we_n=1, bank=0b100, address=0b10000000000)
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precharge = dict(cs_n=0, cas_n=1, ras_n=0, we_n=0, bank=0b011, address=0)
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mrw = dict(cs_n=0, cas_n=0, ras_n=0, we_n=0, bank=0b110011, address=0b10101010) # bank=6-bit address, address=8-bit op code
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zqc_start = dict(cs_n=0, cas_n=1, ras_n=1, we_n=0, bank=0, address=0b1001111) # MPC with ZQCAL START operand
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zqc_latch = dict(cs_n=0, cas_n=1, ras_n=1, we_n=0, bank=0, address=0b1010001) # MPC with ZQCAL LATCH operand
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mrr = dict(cs_n=0, cas_n=1, ras_n=1, we_n=0, bank=1, address=0b101101) # 6-bit address (bank=1 selects MRR)
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for masked_write in [True, False]:
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with self.subTest(masked_write=masked_write):
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wr_ca3 = '{}x00'.format('0' if not masked_write else '1')
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ, masked_write=masked_write),
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dfi_sequence = [
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{0: read, 4: write_ap},
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{0: activate, 4: refresh_ab},
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{0: precharge, 4: mrw},
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{0: zqc_start, 4: zqc_latch},
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{0: mrr},
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],
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pad_checkers = {"sys8x_90": {
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# note that refresh and precharge have a single command so these go as cmd2
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# here MRR CAS-2 is sent with C[8:2] also taken from dfi.address, but this should have no influence
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# rd wr act ref pre mrw zqcs zqcl mrr
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'cs': latency + '1010'+'1010' + '1010'+'0010' + '0010'+'1010' + '0010'+'0010' + '1010'+'0000',
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'ca0': latency + '0100'+'0100' + '1011'+'0000' + '0001'+'0100' + '0001'+'0001' + '0101'+'0000',
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'ca1': latency + '1010'+'0110' + '0110'+'0000' + '0001'+'1111' + '0001'+'0000' + '1011'+'0000',
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'ca2': latency + '0101'+'1100' + '0010'+'0001' + '0000'+'1010' + '0001'+'0000' + '1100'+'0000',
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'ca3': latency + '0x01'+wr_ca3 + '1110'+'001x' + '000x'+'0001' + '0001'+'0000' + '1101'+'0000',
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'ca4': latency + '0110'+'0010' + '1010'+'000x' + '001x'+'0110' + '0000'+'0001' + '0010'+'0000',
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'ca5': latency + '0010'+'0100' + '1001'+'001x' + '000x'+'1101' + '0010'+'0010' + 'x100'+'0000',
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}},
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)
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def test_lpddr4_command_overlaps(self):
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# Test command overlap protection (can happen only if controller violates timings)
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latency = '00000000' * self.CMD_LATENCY
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read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)
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dfi_sequence = [
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# p2 always ignored:
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# 1111
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# 1111
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# 1111
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{0: read, 2: read, 6: read},
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{},
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# p2 or both p2 and p4 ignored, depending on extended_overlaps_check
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# 1111
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# 1111
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# 1111
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{0: read, 2: read, 4: read},
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]
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for extended_check in [False, True]:
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with self.subTest(extended_check=extended_check):
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phy = LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ, extended_overlaps_check=extended_check)
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pads = {
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False: {'cs': latency + '10100010'+'10000000'+'10100000'}, # last cycle: p2 and p4 ignored
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True: {'cs': latency + '10100010'+'10000000'+'10101010'}, # last cycle: only p2 ignored
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}[extended_check]
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self.run_test(phy,
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dfi_sequence = dfi_sequence,
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pad_checkers = {"sys8x_90": pads},
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)
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def test_lpddr4_command_pads(self):
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# Test serialization of DFI command pins (cs/cke/odt/reset_n)
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latency = '00000000' * self.CMD_LATENCY
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read = dict(cs_n=0, cas_n=0, ras_n=1, we_n=1)
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = [
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{
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0: dict(cke=1, odt=1, reset_n=1, **read),
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7: dict(cke=0, odt=1, reset_n=1, **read),
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},
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{
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3: dict(cke=1, odt=0, reset_n=0, **read),
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}
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],
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pad_checkers = {"sys8x_90": {
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'cs': latency + '10100001' + '01010100',
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'cke': latency + '10000000' + '00010000',
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'odt': latency + '10000001' + '00000000',
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'reset_n': latency + '11111111' + '11101111',
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}},
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)
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def test_lpddr4_dq_out(self):
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# Test serialization of dfi wrdata to DQ pads
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dut = LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ)
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zero = '00000000' * 2 # zero for 1 sysclk clock in sys8x_ddr clock domain
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dfi_data = {
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0: dict(wrdata=0x11112222),
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1: dict(wrdata=0x33334444),
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2: dict(wrdata=0x55556666),
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3: dict(wrdata=0x77778888),
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4: dict(wrdata=0x9999aaaa),
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5: dict(wrdata=0xbbbbcccc),
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6: dict(wrdata=0xddddeeee),
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7: dict(wrdata=0xffff0000),
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}
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dfi_wrdata_en = {0: dict(wrdata_en=1)} # wrdata_en=1 required on any single phase
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self.run_test(dut,
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dfi_sequence = [dfi_wrdata_en, {}, dfi_data],
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pad_checkers = {"sys8x_90_ddr": {
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f'dq{i}': (self.CMD_LATENCY+1)*zero + zero + dq_pattern(i, dfi_data, "wrdata") + zero for i in range(16)
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}},
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)
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def test_lpddr4_dq_only_1cycle(self):
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# Test that DQ data is sent to pads only during expected cycle, on other cycles there is no data
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dut = LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ)
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zero = '00000000' * 2
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dfi_data = {
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0: dict(wrdata=0x11112222),
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1: dict(wrdata=0x33334444),
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2: dict(wrdata=0x55556666),
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3: dict(wrdata=0x77778888),
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4: dict(wrdata=0x9999aaaa),
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5: dict(wrdata=0xbbbbcccc),
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6: dict(wrdata=0xddddeeee),
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7: dict(wrdata=0xffff0000),
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}
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dfi_wrdata_en = copy.deepcopy(dfi_data)
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dfi_wrdata_en[0].update(dict(wrdata_en=1))
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self.run_test(dut,
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dfi_sequence = [dfi_wrdata_en, dfi_data, dfi_data],
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pad_checkers = {"sys8x_90_ddr": {
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f'dq{i}': (self.CMD_LATENCY+1)*zero + zero + dq_pattern(i, dfi_data, "wrdata") + zero for i in range(16)
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}},
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)
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def test_lpddr4_dqs(self):
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# Test serialization of DQS pattern in relation to DQ data, with proper preamble and postamble
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zero = '00000000' * 2
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = [
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{0: dict(wrdata_en=1)},
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{},
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{ # to get 10101010... pattern on dq0 and only 1s on others
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0: dict(wrdata=0xfffeffff),
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1: dict(wrdata=0xfffeffff),
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2: dict(wrdata=0xfffeffff),
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3: dict(wrdata=0xfffeffff),
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4: dict(wrdata=0xfffeffff),
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5: dict(wrdata=0xfffeffff),
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6: dict(wrdata=0xfffeffff),
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7: dict(wrdata=0xfffeffff),
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},
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],
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pad_checkers = {
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"sys8x_90_ddr": {
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'dq0': (self.CMD_LATENCY+1)*zero + '00000000'+'00000000' + '10101010'+'10101010' + '00000000'+'00000000' + zero,
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'dq1': (self.CMD_LATENCY+1)*zero + '00000000'+'00000000' + '11111111'+'11111111' + '00000000'+'00000000' + zero,
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},
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"sys8x_ddr": { # preamble, pattern, preamble
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'dqs0': (self.CMD_LATENCY+1)*zero + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
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'dqs1': (self.CMD_LATENCY+1)*zero + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
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}
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},
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)
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def test_lpddr4_dmi_no_mask(self):
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# Test proper output on DMI pads. We don't implement masking now, so nothing should be sent to DMI pads
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zero = '00000000' * 2
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = [
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{0: dict(wrdata_en=1)},
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{},
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{
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0: dict(wrdata=0xffffffff),
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1: dict(wrdata=0xffffffff),
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2: dict(wrdata=0xffffffff),
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3: dict(wrdata=0xffffffff),
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4: dict(wrdata=0xffffffff),
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5: dict(wrdata=0xffffffff),
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6: dict(wrdata=0xffffffff),
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7: dict(wrdata=0xffffffff),
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},
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],
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pad_checkers = {
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"sys8x_90_ddr": {
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'dq0': (self.CMD_LATENCY+1)*zero + zero + '11111111'+'11111111' + 2*zero,
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},
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"sys8x_ddr": {
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'dmi0': (self.CMD_LATENCY+1)*zero + (3 + 1)*zero,
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'dmi1': (self.CMD_LATENCY+1)*zero + (3 + 1)*zero,
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}
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},
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)
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def test_lpddr4_dq_in_rddata_valid(self):
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# Test that rddata_valid is set with correct delay
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read_latency = 9 # settings.read_latency
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dfi_sequence = [
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{0: dict(rddata_en=1)}, # command is issued by MC (appears on next cycle)
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*[{p: dict(rddata_valid=0) for p in range(8)} for _ in range(read_latency - 1)], # nothing is sent during write latency
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{p: dict(rddata_valid=1) for p in range(8)},
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{},
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]
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self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
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dfi_sequence = dfi_sequence,
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pad_checkers = {},
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pad_generators = {},
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)
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def test_lpddr4_dq_in_rddata(self):
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# Test that data on DQ pads is deserialized correctly to DFI rddata.
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# We assume that when there are no commands, PHY will still still deserialize the data,
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# which is generally true (tristate oe is 0 whenever we are not writing).
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dfi_data = {
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0: dict(rddata=0x11112222),
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1: dict(rddata=0x33334444),
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2: dict(rddata=0x55556666),
|
|
3: dict(rddata=0x77778888),
|
|
4: dict(rddata=0x9999aaaa),
|
|
5: dict(rddata=0xbbbbcccc),
|
|
6: dict(rddata=0xddddeeee),
|
|
7: dict(rddata=0xffff0000),
|
|
}
|
|
|
|
def sim_dq(pads):
|
|
for _ in range(16 * 1): # wait 1 sysclk cycle
|
|
yield
|
|
for cyc in range(16): # send a burst of data on pads
|
|
for bit in range(16):
|
|
yield pads.dq_i[bit].eq(int(dq_pattern(bit, dfi_data, "rddata")[cyc]))
|
|
yield
|
|
for bit in range(16):
|
|
yield pads.dq_i[bit].eq(0)
|
|
yield
|
|
|
|
read_des_delay = 3 # phy.read_des_delay
|
|
dfi_sequence = [
|
|
{}, # wait 1 sysclk cycle
|
|
*[{} for _ in range(read_des_delay)],
|
|
dfi_data,
|
|
{},
|
|
]
|
|
|
|
self.run_test(LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ),
|
|
dfi_sequence = dfi_sequence,
|
|
pad_checkers = {},
|
|
pad_generators = {
|
|
"sys8x_90_ddr": sim_dq,
|
|
},
|
|
)
|
|
|
|
def test_lpddr4_cmd_write(self):
|
|
# Test whole WRITE command sequence verifying data on pads and write_latency from MC perspective
|
|
for masked_write in [True, False]:
|
|
with self.subTest(masked_write=masked_write):
|
|
phy = LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ, masked_write=masked_write)
|
|
zero = '00000000' * 2
|
|
write_latency = phy.settings.write_latency
|
|
wrphase = phy.settings.wrphase.reset.value
|
|
|
|
dfi_data = {
|
|
0: dict(wrdata=0x11112222),
|
|
1: dict(wrdata=0x33334444),
|
|
2: dict(wrdata=0x55556666),
|
|
3: dict(wrdata=0x77778888),
|
|
4: dict(wrdata=0x9999aaaa),
|
|
5: dict(wrdata=0xbbbbcccc),
|
|
6: dict(wrdata=0xddddeeee),
|
|
7: dict(wrdata=0xffff0000),
|
|
}
|
|
dfi_sequence = [
|
|
{wrphase: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
|
|
*[{} for _ in range(write_latency - 1)],
|
|
dfi_data,
|
|
{},
|
|
{},
|
|
{},
|
|
{},
|
|
{},
|
|
]
|
|
|
|
wr_ca3 = "0000{}000".format('0' if not masked_write else '1')
|
|
self.run_test(phy,
|
|
dfi_sequence = dfi_sequence,
|
|
pad_checkers = {
|
|
"sys8x_90": {
|
|
"cs": "00000000"*2 + "00001010" + "00000000"*2,
|
|
"ca0": "00000000"*2 + "00000000" + "00000000"*2,
|
|
"ca1": "00000000"*2 + "00000010" + "00000000"*2,
|
|
"ca2": "00000000"*2 + "00001000" + "00000000"*2,
|
|
"ca3": "00000000"*2 + wr_ca3 + "00000000"*2,
|
|
"ca4": "00000000"*2 + "00000010" + "00000000"*2,
|
|
"ca5": "00000000"*2 + "00000000" + "00000000"*2,
|
|
},
|
|
"sys8x_90_ddr": {
|
|
f'dq{i}': (self.CMD_LATENCY+1)*zero + zero + dq_pattern(i, dfi_data, "wrdata") + zero
|
|
for i in range(16)
|
|
},
|
|
"sys8x_ddr": {
|
|
"dqs0": (self.CMD_LATENCY+1)*zero + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
|
|
},
|
|
},
|
|
)
|
|
|
|
def test_lpddr4_cmd_read(self):
|
|
# Test whole READ command sequence simulating DRAM response and verifying read_latency from MC perspective
|
|
phy = LPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ)
|
|
zero = '00000000' * 2
|
|
read_latency = phy.settings.read_latency
|
|
rdphase = phy.settings.rdphase.reset.value
|
|
|
|
# FIXME: The data will appear 1 cycle before rddata_valid. This is because we have one more cycle
|
|
# of read latency that is needed for bitslips to be usable, and here we're not doing read leveling
|
|
# so the bitslip is configured incorrectly. If we increased cl by 1 in Simulator and did a single
|
|
# bitslip increment before the test, it should work, but this would unnecessarily complicate the test.
|
|
dfi_data = {
|
|
0: dict(rddata=0x11112222),
|
|
1: dict(rddata=0x33334444),
|
|
2: dict(rddata=0x55556666),
|
|
3: dict(rddata=0x77778888),
|
|
4: dict(rddata=0x9999aaaa),
|
|
5: dict(rddata=0xbbbbcccc),
|
|
6: dict(rddata=0xddddeeee),
|
|
7: dict(rddata=0xffff0000),
|
|
}
|
|
dfi_data_valid = {
|
|
0: dict(rddata_valid=1),
|
|
1: dict(rddata_valid=1),
|
|
2: dict(rddata_valid=1),
|
|
3: dict(rddata_valid=1),
|
|
4: dict(rddata_valid=1),
|
|
5: dict(rddata_valid=1),
|
|
6: dict(rddata_valid=1),
|
|
7: dict(rddata_valid=1),
|
|
}
|
|
dfi_sequence = [
|
|
{rdphase: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, rddata_en=1)},
|
|
*[{} for _ in range(read_latency - 1 - 1)],
|
|
dfi_data,
|
|
dfi_data_valid,
|
|
{},
|
|
{},
|
|
{},
|
|
{},
|
|
]
|
|
|
|
class Simulator:
|
|
def __init__(self, dfi_data, test_case, cl):
|
|
self.dfi_data = dfi_data
|
|
self.read_cmd = False
|
|
self.test_case = test_case
|
|
self.cl = cl
|
|
|
|
@passive
|
|
def cmd_checker(self, pads):
|
|
# Monitors CA/CS for a READ command
|
|
read = [
|
|
0b000010, # READ-1 (1) BL=0
|
|
0b000000, # READ-1 (2) BA=0, C9=0, AP=0
|
|
0b010010, # CAS-2 (1) C8=0
|
|
0b000000, # CAS-2 (2) C=0
|
|
]
|
|
|
|
def check_ca(i):
|
|
err = "{}: CA = 0b{:06b}, expected = 0b{:06b}".format(i, (yield pads.ca), read[i])
|
|
self.test_case.assertEqual((yield pads.ca), read[i], msg=err)
|
|
|
|
while True:
|
|
while not (yield pads.cs):
|
|
yield
|
|
yield from check_ca(0)
|
|
yield
|
|
yield from check_ca(1)
|
|
yield
|
|
self.test_case.assertEqual((yield pads.cs), 1, msg="Found CS on 1st cycle but not on 3rd cycle")
|
|
yield from check_ca(2)
|
|
yield
|
|
yield from check_ca(3)
|
|
self.read_cmd = True
|
|
|
|
@passive
|
|
def dq_generator(self, pads):
|
|
# After a READ command is received, wait CL and send data
|
|
while True:
|
|
while not self.read_cmd:
|
|
yield
|
|
dfi_data = self.dfi_data.pop(0)
|
|
for _ in range(2*self.cl + 1):
|
|
yield
|
|
self.read_cmd = False
|
|
for cyc in range(16):
|
|
for bit in range(16):
|
|
yield pads.dq_i[bit].eq(int(dq_pattern(bit, dfi_data, "rddata")[cyc]))
|
|
yield
|
|
for bit in range(16):
|
|
yield pads.dq_i[bit].eq(0)
|
|
|
|
@passive
|
|
def dqs_generator(self, pads):
|
|
# After a READ command is received, wait CL and send data strobe
|
|
while True:
|
|
while not self.read_cmd:
|
|
yield
|
|
for _ in range(2*self.cl - 1): # DQS to transmit DQS preamble
|
|
yield
|
|
for cyc in range(16 + 1): # send a burst of data on pads
|
|
for bit in range(2):
|
|
yield pads.dqs_i[bit].eq(int((cyc + 1) % 2))
|
|
yield
|
|
for bit in range(2):
|
|
yield pads.dqs_i[bit].eq(0)
|
|
|
|
sim = Simulator([dfi_data], self, cl=14)
|
|
self.run_test(phy,
|
|
dfi_sequence = dfi_sequence,
|
|
pad_checkers = {
|
|
"sys8x_90": {
|
|
"cs": "00000000"*2 + rdphase*"0" + "1010" + "00000000"*2,
|
|
"ca0": "00000000"*2 + rdphase*"0" + "0000" + "00000000"*2,
|
|
"ca1": "00000000"*2 + rdphase*"0" + "1010" + "00000000"*2,
|
|
"ca2": "00000000"*2 + rdphase*"0" + "0000" + "00000000"*2,
|
|
"ca3": "00000000"*2 + rdphase*"0" + "0000" + "00000000"*2,
|
|
"ca4": "00000000"*2 + rdphase*"0" + "0010" + "00000000"*2,
|
|
"ca5": "00000000"*2 + rdphase*"0" + "0000" + "00000000"*2,
|
|
},
|
|
"sys8x_90_ddr": { #?
|
|
f'dq{i}': (self.CMD_LATENCY+2)*zero + zero + dq_pattern(i, dfi_data, "rddata") + zero
|
|
for i in range(16)
|
|
},
|
|
"sys8x_ddr": {
|
|
"dqs0": (self.CMD_LATENCY+2)*zero + '00000000'+'00000001' + '01010101'+'01010101' + zero,
|
|
},
|
|
},
|
|
pad_generators = {
|
|
"sys8x_ddr": [sim.dq_generator, sim.dqs_generator],
|
|
"sys8x_90": sim.cmd_checker,
|
|
},
|
|
)
|
|
|
|
def test_lpddr4_double_rate_phy_write(self):
|
|
# Verify that double rate PHY works as normal one with half sys clock more latency
|
|
phy = DoubleRateLPDDR4SimPHY(sys_clk_freq=self.SYS_CLK_FREQ, serdes_reset_cnt=-1)
|
|
zero = '00000000' * 2 # DDR
|
|
half = '0000' # double rate PHY introduces latency of 4 sys8x clocks
|
|
init_ddr_latency = (self.CMD_LATENCY + 1) * zero + half*2 # half*2 for DDR
|
|
write_latency = phy.settings.write_latency
|
|
wrphase = phy.settings.wrphase.reset.value
|
|
|
|
dfi_data = {
|
|
0: dict(wrdata=0x11112222),
|
|
1: dict(wrdata=0x33334444),
|
|
2: dict(wrdata=0x55556666),
|
|
3: dict(wrdata=0x77778888),
|
|
4: dict(wrdata=0x9999aaaa),
|
|
5: dict(wrdata=0xbbbbcccc),
|
|
6: dict(wrdata=0xddddeeee),
|
|
7: dict(wrdata=0xffff0000),
|
|
}
|
|
dfi_sequence = [
|
|
{wrphase: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
|
|
*[{} for _ in range(write_latency - 1)],
|
|
dfi_data,
|
|
{},
|
|
{},
|
|
{},
|
|
{},
|
|
{},
|
|
]
|
|
|
|
self.run_test(phy,
|
|
dfi_sequence = dfi_sequence,
|
|
pad_checkers = {
|
|
"sys8x_90": {
|
|
"cs": half + "00000000"*2 + "00001010" + "00000000"*2,
|
|
"ca0": half + "00000000"*2 + "00000000" + "00000000"*2,
|
|
"ca1": half + "00000000"*2 + "00000010" + "00000000"*2,
|
|
"ca2": half + "00000000"*2 + "00001000" + "00000000"*2,
|
|
"ca3": half + "00000000"*2 + "00001000" + "00000000"*2,
|
|
"ca4": half + "00000000"*2 + "00000010" + "00000000"*2,
|
|
"ca5": half + "00000000"*2 + "00000000" + "00000000"*2,
|
|
},
|
|
"sys8x_90_ddr": {
|
|
f'dq{i}': init_ddr_latency + zero + dq_pattern(i, dfi_data, "wrdata") + zero
|
|
for i in range(16)
|
|
},
|
|
"sys8x_ddr": {
|
|
"dqs0": init_ddr_latency + '01010101'+'00000101' + '01010101'+'01010101' + '00010101'+'01010101' + zero,
|
|
},
|
|
},
|
|
)
|
|
|
|
|
|
# Named regex group
|
|
def ng(name, regex):
|
|
return r"(?P<{}>{})".format(name, regex)
|
|
|
|
|
|
class VerilatorLPDDR4Tests(unittest.TestCase):
|
|
LOG_PATTERN = re.compile(r"\[\s*{time} ps] \[{level}]\s*{msg}".format(
|
|
time = ng("time", r"[0-9]+"),
|
|
level = ng("level", r"DEBUG|INFO|WARN|ERROR"),
|
|
msg = ng("msg", ".*"),
|
|
))
|
|
|
|
# We ignore these 2 warnings, they appear due to the fact that litedram starts
|
|
# in hardware control mode which holds reset_n=1 all the time. PHY will later
|
|
# set reset_n=0 once again and then perform proper init sequence.
|
|
ALLOWED = [
|
|
("WARN", "tINIT1 violated: RESET deasserted too fast"),
|
|
("WARN", "tINIT3 violated: CKE set HIGH too fast after RESET being released"),
|
|
]
|
|
|
|
def check_logs(self, logs):
|
|
for match in self.LOG_PATTERN.finditer(logs):
|
|
if match.group("level") in ["WARN", "ERROR"]:
|
|
allowed = any(
|
|
lvl == match.group("level") and msg in match.group("msg")
|
|
for lvl, msg in self.ALLOWED
|
|
)
|
|
self.assertTrue(allowed, msg=match.group(0))
|
|
|
|
def run_test(self, args, **kwargs):
|
|
import pexpect
|
|
|
|
command = ["python3", simsoc.__file__, *args]
|
|
timeout = 12 * 60 # give more than enough time
|
|
p = pexpect.spawn(" ".join(command), timeout=timeout, **kwargs)
|
|
|
|
res = p.expect(["Memtest OK", "Memtest KO"])
|
|
self.assertEqual(res, 0, msg="{}\nGot '{}'".format(p.before.decode(), p.after.decode()))
|
|
|
|
self.check_logs(p.before.decode())
|
|
|
|
def test_lpddr4_sim_x2rate_no_cache(self):
|
|
# Test simulation with regular delays, intermediate serialization stage,
|
|
# refresh and no L2 cache (masked write must work)
|
|
self.run_test([
|
|
"--finish-after-memtest", "--log-level", "warn",
|
|
"--double-rate-phy",
|
|
"--l2-size", "0",
|
|
"--no-refresh", # FIXME: LiteDRAM sends refresh commands when only MRW/MRR are allowed
|
|
])
|
|
|
|
def test_lpddr4_sim_fast(self):
|
|
# Fast test of simulation with L2 cache (so no data masking is required)
|
|
self.run_test([
|
|
"--finish-after-memtest", "--log-level", "warn",
|
|
"--disable-delay",
|
|
"--no-refresh",
|
|
])
|