Jędrzej Boczar 914d018cf8 phy/sim_utils: support low wait times (0/1) in PulseTiming		2021-10-26 12:22:30 +02:00
..
primitives	…
reference	test: update *_init.h reference	2021-08-04 12:30:56 +02:00
spd_data	…
summary	…
__init__.py	…
access_pattern.csv	…
benchmark.py	…
benchmarks.yml	…
common.py	…
gen_access_pattern.py	…
gen_config.py	…
phy_common.py	phy/utils: DFI rate converter for creating PHY wrappers at slower clocks	2021-08-04 12:30:56 +02:00
run_benchmarks.py	…
test_adaptation.py	…
test_adapter.py	…
test_axi.py	…
test_bandwidth.py	…
test_bankmachine.py	…
test_bist.py	…
test_command_chooser.py	…
test_crossbar.py	…
test_dfi.py	phy/utils: DFI rate converter for creating PHY wrappers at slower clocks	2021-08-04 12:30:56 +02:00
test_dma.py	…
test_ecc.py	test/test_ecc: Update.	2021-06-08 15:07:39 +02:00
test_examples.py	litedram_gen: Add initial SDRAM support (with ULX3S example).	2021-07-02 09:01:31 +02:00
test_fifo.py	frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width.	2021-10-06 18:05:48 +02:00
test_init.py	test/test_init: Add simple way to update references.	2021-05-18 11:26:19 +02:00
test_lpddr4.py	phy/lpddr4/simsoc: Change cpu_variant to lite and revert commented test_lpddr4_sim_x2rate_no_cache.	2021-07-02 09:24:11 +02:00
test_lpddr5.py	phy/lpddr5: add simulation SoC	2021-10-26 12:22:30 +02:00
test_modules.py	…
test_multiplexer.py	…
test_phy_utils.py	test/phy_common: simplify calls to run_simulation	2021-06-22 11:41:44 +02:00
test_refresh.py	…
test_sim_utils.py	phy/sim_utils: support low wait times (0/1) in PulseTiming	2021-10-26 12:22:30 +02:00
test_steerer.py	…
test_timing.py	…
test_wishbone.py	…