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phy/lpddr4/simsoc: Change cpu_variant to lite and revert commented test_lpddr4_sim_x2rate_no_cache. 

(see #255).
This commit is contained in:
Florent Kermarrec 2021-07-02 09:24:11 +02:00
parent a11d1b870d
commit a3aa4907f1
2 changed files with 10 additions and 10 deletions
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2
litedram/phy/lpddr4/simsoc.py
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@ -123,7 +123,7 @@ class SimSoC(SoCCore):
clk_freq = sys_clk_freq,
ident = "LiteX Simulation",
ident_version = True,
cpu_variant = "minimal",
cpu_variant = "lite",
**kwargs)
# CRG --------------------------------------------------------------------------------------

18
test/test_lpddr4.py
View File

@ -692,15 +692,15 @@ class VerilatorLPDDR4Tests(unittest.TestCase):
self.check_logs(p.before.decode())
#def test_lpddr4_sim_x2rate_no_cache(self):
# # Test simulation with regular delays, intermediate serialization stage,
# # refresh and no L2 cache (masked write must work)
# self.run_test([
# "--finish-after-memtest", "--log-level", "warn",
# "--double-rate-phy",
# "--l2-size", "0",
# "--no-refresh", # FIXME: LiteDRAM sends refresh commands when only MRW/MRR are allowed
# ])
def test_lpddr4_sim_x2rate_no_cache(self):
# Test simulation with regular delays, intermediate serialization stage,
# refresh and no L2 cache (masked write must work)
self.run_test([
"--finish-after-memtest", "--log-level", "warn",
"--double-rate-phy",
"--l2-size", "0",
"--no-refresh", # FIXME: LiteDRAM sends refresh commands when only MRW/MRR are allowed
])
def test_lpddr4_sim_fast(self):
# Fast test of simulation with L2 cache (so no data masking is required)