734 lines
26 KiB
Python
734 lines
26 KiB
Python
#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2016 Tim 'mithro' Ansell <mithro@mithis.com>
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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import random
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import itertools
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from functools import partial
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from operator import or_
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from migen import *
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def seed_to_data(seed, random=True, nbits=32):
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if nbits == 32:
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if random:
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return (seed * 0x31415979 + 1) & 0xffffffff
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else:
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return seed
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else:
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assert nbits%32 == 0
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data = 0
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for i in range(nbits//32):
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data = data << 32
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data |= seed_to_data(seed*nbits//32 + i, random, 32)
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return data
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@passive
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def timeout_generator(ticks):
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# raise exception after given timeout effectively stopping simulation
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# because of @passive, simulation can end even if this generator is still running
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for _ in range(ticks):
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yield
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raise TimeoutError("Timeout after %d ticks" % ticks)
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class NativePortDriver:
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"""Generates sequences for reading/writing to LiteDRAMNativePort
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The write/read versions with wait_data=False are a cheap way to perform
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burst during which the port is being held locked, but this way all the
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data is being lost (would require separate coroutine to handle data).
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"""
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def __init__(self, port):
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self.port = port
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self.wdata = [] # fifo, consumed by handler
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self.rdata = [] # stack, never consumed
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self.rdata_expected = 0
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def generators(self):
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return [self.write_data_handler(), self.read_data_handler()]
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def wait_all(self):
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while self.wdata or len(self.rdata) < self.rdata_expected:
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yield
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@passive
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def write_data_handler(self):
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while True:
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if self.wdata:
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# pop the data only after write has been completed
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data, we = self.wdata[0]
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yield self.port.wdata.valid.eq(1)
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yield self.port.wdata.data.eq(data)
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yield self.port.wdata.we.eq(we)
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yield
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while (yield self.port.wdata.ready) == 0:
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yield
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yield self.port.wdata.valid.eq(0)
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self.wdata.pop(0)
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yield
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@passive
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def read_data_handler(self, latency=0):
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if latency == 0:
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yield self.port.rdata.ready.eq(1)
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while True:
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while (yield self.port.rdata.valid) == 0:
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yield
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data = (yield self.port.rdata.data)
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yield
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self.rdata.append(data)
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else:
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while True:
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while (yield self.port.rdata.valid) == 0:
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yield
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data = (yield self.port.rdata.data)
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yield self.port.rdata.ready.eq(1)
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yield
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self.rdata.append(data)
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yield self.port.rdata.ready.eq(0)
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for _ in range(latency):
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yield
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def read(self, address, first=0, last=0, wait_data=True):
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yield self.port.cmd.valid.eq(1)
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yield self.port.cmd.first.eq(first)
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yield self.port.cmd.last.eq(last)
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yield self.port.cmd.we.eq(0)
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yield self.port.cmd.addr.eq(address)
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yield
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while (yield self.port.cmd.ready) == 0:
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yield
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self.rdata_expected += 1
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yield self.port.cmd.valid.eq(0)
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if wait_data:
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while len(self.rdata) != self.rdata_expected:
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yield
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return self.rdata[-1]
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def write(self, address, data, we=None, first=0, last=0, wait_data=True, data_with_cmd=False):
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if we is None:
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we = 2**self.port.wdata.we.nbits - 1
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yield self.port.cmd.valid.eq(1)
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yield self.port.cmd.first.eq(first)
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yield self.port.cmd.last.eq(last)
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yield self.port.cmd.we.eq(1)
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yield self.port.cmd.addr.eq(address)
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if data_with_cmd:
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self.wdata.append((data, we))
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yield
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while (yield self.port.cmd.ready) == 0:
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yield
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if not data_with_cmd:
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self.wdata.append((data, we))
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yield self.port.cmd.valid.eq(0)
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if wait_data:
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n_wdata = len(self.wdata)
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while len(self.wdata) != n_wdata - 1:
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yield
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class CmdRequestRWDriver:
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"""Simple driver for Endpoint(cmd_request_rw_layout())"""
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def __init__(self, req, i=0, ep_layout=True, rw_layout=True):
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self.req = req
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self.rw_layout = rw_layout # if False, omit is_* signals
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self.ep_layout = ep_layout # if False, omit endpoint signals (valid, etc.)
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# used to distinguish commands
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self.i = self.bank = self.row = self.col = i
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def request(self, char):
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# convert character to matching command invocation
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return {
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"w": self.write,
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"r": self.read,
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"W": partial(self.write, auto_precharge=True),
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"R": partial(self.read, auto_precharge=True),
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"a": self.activate,
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"p": self.precharge,
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"f": self.refresh,
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"_": self.nop,
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}[char]()
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def activate(self):
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yield from self._drive(valid=1, is_cmd=1, ras=1, a=self.row, ba=self.bank)
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def precharge(self, all_banks=False):
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a = 0 if not all_banks else (1 << 10)
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yield from self._drive(valid=1, is_cmd=1, ras=1, we=1, a=a, ba=self.bank)
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def refresh(self):
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yield from self._drive(valid=1, is_cmd=1, cas=1, ras=1, ba=self.bank)
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def write(self, auto_precharge=False):
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assert not (self.col & (1 << 10))
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col = self.col | (1 << 10) if auto_precharge else self.col
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yield from self._drive(valid=1, is_write=1, cas=1, we=1, a=col, ba=self.bank)
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def read(self, auto_precharge=False):
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assert not (self.col & (1 << 10))
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col = self.col | (1 << 10) if auto_precharge else self.col
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yield from self._drive(valid=1, is_read=1, cas=1, a=col, ba=self.bank)
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def nop(self):
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yield from self._drive()
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def _drive(self, **kwargs):
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signals = ["a", "ba", "cas", "ras", "we"]
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if self.rw_layout:
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signals += ["is_cmd", "is_read", "is_write"]
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if self.ep_layout:
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signals += ["valid", "first", "last"]
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for s in signals:
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yield getattr(self.req, s).eq(kwargs.get(s, 0))
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# drive ba even for nop, to be able to distinguish bank machines anyway
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if "ba" not in kwargs:
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yield self.req.ba.eq(self.bank)
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class DRAMMemory:
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def __init__(self, width, depth, init=[]):
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self.width = width
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self.depth = depth
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self.mem = []
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for d in init:
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self.mem.append(d)
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for _ in range(depth-len(init)):
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self.mem.append(0)
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# "W" enables write msgs, "R" - read msgs and "1" both
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self._debug = os.environ.get("DRAM_MEM_DEBUG", "0")
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def show_content(self):
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for addr in range(self.depth):
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print("0x{:08x}: 0x{:0{dwidth}x}".format(addr, self.mem[addr], dwidth=self.width//4))
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def _warn(self, address):
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if address > self.depth * self.width:
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print("! adr > 0x{:08x}".format(
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self.depth * self.width))
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def _write(self, address, data, we):
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mask = reduce(or_, [0xff << (8 * bit) for bit in range(self.width//8)
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if (we & (1 << bit)) != 0], 0)
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data = data & mask
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self.mem[address%self.depth] = data | (self.mem[address%self.depth] & ~mask)
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if self._debug in ["1", "W"]:
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print("W 0x{:08x}: 0x{:0{dwidth}x}".format(address, self.mem[address%self.depth],
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dwidth=self.width//4))
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self._warn(address)
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def _read(self, address):
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if self._debug in ["1", "R"]:
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print("R 0x{:08x}: 0x{:0{dwidth}x}".format(address, self.mem[address%self.depth],
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dwidth=self.width//4))
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self._warn(address)
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return self.mem[address%self.depth]
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@passive
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def read_handler(self, dram_port, rdata_valid_random=0):
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address = 0
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pending = 0
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prng = random.Random(42)
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yield dram_port.cmd.ready.eq(0)
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while True:
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yield dram_port.rdata.valid.eq(0)
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if pending:
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while prng.randrange(100) < rdata_valid_random:
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yield
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yield dram_port.rdata.valid.eq(1)
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yield dram_port.rdata.data.eq(self._read(address))
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yield
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yield dram_port.rdata.valid.eq(0)
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yield dram_port.rdata.data.eq(0)
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pending = 0
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elif (yield dram_port.cmd.valid):
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pending = not (yield dram_port.cmd.we)
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address = (yield dram_port.cmd.addr)
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if pending:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield dram_port.cmd.ready.eq(0)
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yield
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@passive
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def write_handler(self, dram_port, wdata_ready_random=0):
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address = 0
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pending = 0
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prng = random.Random(42)
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yield dram_port.cmd.ready.eq(0)
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while True:
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yield dram_port.wdata.ready.eq(0)
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if pending:
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while (yield dram_port.wdata.valid) == 0:
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yield
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while prng.randrange(100) < wdata_ready_random:
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yield
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yield dram_port.wdata.ready.eq(1)
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yield
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self._write(address, (yield dram_port.wdata.data), (yield dram_port.wdata.we))
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yield dram_port.wdata.ready.eq(0)
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yield
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pending = 0
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yield
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elif (yield dram_port.cmd.valid):
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pending = (yield dram_port.cmd.we)
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address = (yield dram_port.cmd.addr)
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if pending:
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yield dram_port.cmd.ready.eq(1)
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yield
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yield dram_port.cmd.ready.eq(0)
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yield
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class MemoryTestDataMixin:
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@property
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def bist_test_data(self):
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data = {
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"8bit": dict(
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base = 2,
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end = 2 + 8, # (end - base) must be pow of 2
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length = 5,
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# 2 3 4 5 6 7=2+5
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expected = [0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x00],
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),
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"32bit": dict(
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base = 0x04,
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end = 0x04 + 8,
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length = 5 * 4,
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expected = [
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0x00000000, # 0x00
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0x00000000, # 0x04
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0x00000001, # 0x08
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0x00000002, # 0x0c
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0x00000003, # 0x10
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0x00000004, # 0x14
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0x00000000, # 0x18
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0x00000000, # 0x1c
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],
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),
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"64bit": dict(
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base = 0x10,
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end = 0x10 + 8,
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length = 5 * 8,
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expected = [
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0x0000000000000000, # 0x00
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0x0000000000000000, # 0x08
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0x0000000000000000, # 0x10
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0x0000000000000001, # 0x18
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0x0000000000000002, # 0x20
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0x0000000000000003, # 0x28
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0x0000000000000004, # 0x30
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0x0000000000000000, # 0x38
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],
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),
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"32bit_masked": dict(
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base = 0x04,
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end = 0x04 + 0x04, # TODO: fix address masking to be consistent
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length = 6 * 4,
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expected = [ # due to masking
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0x00000000, # 0x00
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0x00000004, # 0x04
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0x00000005, # 0x08
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0x00000002, # 0x0c
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0x00000003, # 0x10
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0x00000000, # 0x14
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0x00000000, # 0x18
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0x00000000, # 0x1c
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],
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),
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}
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data["32bit_long_sequential"] = dict(
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base = 16,
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end = 16 + 128,
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length = 64,
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expected = [0x00000000] * 128
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)
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expected = data["32bit_long_sequential"]["expected"]
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expected[16//4:(16 + 64)//4] = list(range(64//4))
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return data
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@property
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def pattern_test_data(self):
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data = {
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"8bit": dict(
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pattern=[
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# address, data
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(0x00, 0xaa),
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(0x05, 0xbb),
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(0x02, 0xcc),
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(0x07, 0xdd),
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],
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expected=[
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# data, address
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0xaa, # 0x00
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0x00, # 0x01
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0xcc, # 0x02
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0x00, # 0x03
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0x00, # 0x04
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0xbb, # 0x05
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0x00, # 0x06
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0xdd, # 0x07
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],
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),
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"32bit": dict(
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pattern=[
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# address, data
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(0x00, 0xabadcafe),
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(0x07, 0xbaadf00d),
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(0x02, 0xcafefeed),
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(0x01, 0xdeadc0de),
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],
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expected=[
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# data, address
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0xabadcafe, # 0x00
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0xdeadc0de, # 0x04
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0xcafefeed, # 0x08
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0x00000000, # 0x0c
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0x00000000, # 0x10
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0x00000000, # 0x14
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0x00000000, # 0x18
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0xbaadf00d, # 0x1c
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],
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),
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"64bit": dict(
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pattern=[
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# address, data
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(0x00, 0x0ddf00dbadc0ffee),
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(0x05, 0xabadcafebaadf00d),
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(0x02, 0xcafefeedfeedface),
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(0x07, 0xdeadc0debaadbeef),
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],
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expected=[
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# data, address
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0x0ddf00dbadc0ffee, # 0x00
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0x0000000000000000, # 0x08
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0xcafefeedfeedface, # 0x10
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0x0000000000000000, # 0x18
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0x0000000000000000, # 0x20
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0xabadcafebaadf00d, # 0x28
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0x0000000000000000, # 0x30
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0xdeadc0debaadbeef, # 0x38
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],
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),
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"64bit_to_32bit": dict(
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pattern=[
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# address, data
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(0x00, 0x0d15ea5e00facade),
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(0x05, 0xabadcafe8badf00d),
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(0x01, 0xcafefeedbaadf00d),
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(0x02, 0xfee1deaddeadc0de),
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],
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expected=[
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# data, word, address
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0x00facade, # 0 0x00
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0x0d15ea5e, # 1 0x04
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0xbaadf00d, # 2 0x08
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0xcafefeed, # 3 0x0c
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0xdeadc0de, # 4 0x10
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0xfee1dead, # 5 0x14
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0x00000000, # 6 0x18
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0x00000000, # 7 0x1c
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0x00000000, # 8 0x20
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0x00000000, # 9 0x24
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0x8badf00d, # 10 0x28
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0xabadcafe, # 11 0x2c
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0x00000000, # 12 0x30
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]
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),
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"32bit_to_8bit": dict(
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pattern=[
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# address, data
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(0x00, 0x00112233),
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(0x05, 0x44556677),
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(0x01, 0x8899aabb),
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(0x02, 0xccddeeff),
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],
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expected=[
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# data, address
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0x33, # 0x00
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0x22, # 0x01
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0x11, # 0x02
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0x00, # 0x03
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0xbb, # 0x04
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0xaa, # 0x05
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0x99, # 0x06
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0x88, # 0x07
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0xff, # 0x08
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0xee, # 0x09
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0xdd, # 0x0a
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0xcc, # 0x0b
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0x00, # 0x0c
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0x00, # 0x0d
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0x00, # 0x0e
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0x00, # 0x0f
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0x00, # 0x10
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0x00, # 0x11
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0x00, # 0x12
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0x00, # 0x13
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0x77, # 0x14
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0x66, # 0x15
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0x55, # 0x16
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0x44, # 0x17
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0x00, # 0x18
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0x00, # 0x19
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]
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),
|
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"8bit_to_32bit": dict(
|
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pattern=[
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# address, data
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(0x00, 0x00),
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(0x01, 0x11),
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(0x02, 0x22),
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(0x03, 0x33),
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(0x10, 0x44),
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(0x11, 0x55),
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(0x12, 0x66),
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(0x13, 0x77),
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(0x08, 0x88),
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(0x09, 0x99),
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(0x0a, 0xaa),
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(0x0b, 0xbb),
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(0x0c, 0xcc),
|
|
(0x0d, 0xdd),
|
|
(0x0e, 0xee),
|
|
(0x0f, 0xff),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0x33221100, # 0x00
|
|
0x00000000, # 0x04
|
|
0xbbaa9988, # 0x08
|
|
0xffeeddcc, # 0x0c
|
|
0x77665544, # 0x10
|
|
0x00000000, # 0x14
|
|
0x00000000, # 0x18
|
|
0x00000000, # 0x1c
|
|
]
|
|
),
|
|
"8bit_to_32bit_not_aligned": dict(
|
|
pattern=[
|
|
# address, data
|
|
(0x00, 0x00),
|
|
(0x05, 0x11),
|
|
(0x0a, 0x22),
|
|
(0x0f, 0x33),
|
|
(0x1e, 0x44),
|
|
(0x15, 0x55),
|
|
(0x13, 0x66),
|
|
(0x18, 0x77),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0x00000000, # 0x00
|
|
0x00001100, # 0x04
|
|
0x00220000, # 0x08
|
|
0x33000000, # 0x0c
|
|
0x66000000, # 0x10
|
|
0x00005500, # 0x14
|
|
0x00000077, # 0x18
|
|
0x00440000, # 0x1c
|
|
]
|
|
),
|
|
"8bit_to_32bit_not_sequential": dict(
|
|
pattern=[
|
|
# address, data
|
|
(0x03, 0x00),
|
|
(0x02, 0x11),
|
|
(0x01, 0x22),
|
|
(0x00, 0x33),
|
|
(0x12, 0x44),
|
|
(0x11, 0x55),
|
|
(0x13, 0x66),
|
|
(0x10, 0x77),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0x00112233, # 0x00
|
|
0x00000000, # 0x04
|
|
0x00000000, # 0x08
|
|
0x00000000, # 0x0c
|
|
0x66445577, # 0x10
|
|
0x00000000, # 0x14
|
|
0x00000000, # 0x18
|
|
0x00000000, # 0x1c
|
|
]
|
|
),
|
|
"32bit_to_256bit": dict(
|
|
pattern=[
|
|
# address, data
|
|
(0x00, 0x00000000),
|
|
(0x01, 0x11111111),
|
|
(0x02, 0x22222222),
|
|
(0x03, 0x33333333),
|
|
(0x04, 0x44444444),
|
|
(0x05, 0x55555555),
|
|
(0x06, 0x66666666),
|
|
(0x07, 0x77777777),
|
|
(0x10, 0x88888888),
|
|
(0x11, 0x99999999),
|
|
(0x12, 0xaaaaaaaa),
|
|
(0x13, 0xbbbbbbbb),
|
|
(0x14, 0xcccccccc),
|
|
(0x15, 0xdddddddd),
|
|
(0x16, 0xeeeeeeee),
|
|
(0x17, 0xffffffff),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0x7777777766666666555555554444444433333333222222221111111100000000, # 0x00
|
|
0x0000000000000000000000000000000000000000000000000000000000000000, # 0x20
|
|
0xffffffffeeeeeeeeddddddddccccccccbbbbbbbbaaaaaaaa9999999988888888, # 0x40
|
|
0x0000000000000000000000000000000000000000000000000000000000000000, # 0x60
|
|
]
|
|
),
|
|
"8bit_to_256bit": dict(
|
|
# address, data
|
|
pattern=[(i, 0x10 + i) for i in range(128)],
|
|
expected=[
|
|
# data, address
|
|
0x2f2e2d2c2b2a292827262524232221201f1e1d1c1b1a19181716151413121110, # 0x00
|
|
0x4f4e4d4c4b4a494847464544434241403f3e3d3c3b3a39383736353433323130, # 0x20
|
|
0x6f6e6d6c6b6a696867666564636261605f5e5d5c5b5a59585756555453525150, # 0x40
|
|
0x8f8e8d8c8b8a898887868584838281807f7e7d7c7b7a79787776757473727170, # 0x60
|
|
]
|
|
),
|
|
"32bit_to_256bit_not_aligned": dict(
|
|
pattern=[
|
|
# address, data
|
|
(0x00, 0x00000000),
|
|
(0x01, 0x11111111),
|
|
(0x02, 0x22222222),
|
|
(0x03, 0x33333333),
|
|
(0x04, 0x44444444),
|
|
(0x05, 0x55555555),
|
|
(0x06, 0x66666666),
|
|
(0x07, 0x77777777),
|
|
(0x14, 0x88888888),
|
|
(0x15, 0x99999999),
|
|
(0x16, 0xaaaaaaaa),
|
|
(0x17, 0xbbbbbbbb),
|
|
(0x18, 0xcccccccc),
|
|
(0x19, 0xdddddddd),
|
|
(0x1a, 0xeeeeeeee),
|
|
(0x1b, 0xffffffff),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0x7777777766666666555555554444444433333333222222221111111100000000, # 0x00
|
|
0x0000000000000000000000000000000000000000000000000000000000000000, # 0x20
|
|
0xbbbbbbbbaaaaaaaa999999998888888800000000000000000000000000000000, # 0x40
|
|
0x00000000000000000000000000000000ffffffffeeeeeeeeddddddddcccccccc, # 0x60
|
|
]
|
|
),
|
|
"32bit_not_aligned": dict(
|
|
pattern=[
|
|
# address, data
|
|
(0x00, 0xabadcafe),
|
|
(0x07, 0xbaadf00d),
|
|
(0x02, 0xcafefeed),
|
|
(0x01, 0xdeadc0de),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0xabadcafe, # 0x00
|
|
0xdeadc0de, # 0x04
|
|
0xcafefeed, # 0x08
|
|
0x00000000, # 0x0c
|
|
0x00000000, # 0x10
|
|
0x00000000, # 0x14
|
|
0x00000000, # 0x18
|
|
0xbaadf00d, # 0x1c
|
|
],
|
|
),
|
|
"32bit_duplicates": dict(
|
|
pattern=[
|
|
# address, data
|
|
(0x00, 0xabadcafe),
|
|
(0x07, 0xbaadf00d),
|
|
(0x00, 0xcafefeed),
|
|
(0x07, 0xdeadc0de),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0xcafefeed, # 0x00
|
|
0x00000000, # 0x04
|
|
0x00000000, # 0x08
|
|
0x00000000, # 0x0c
|
|
0x00000000, # 0x10
|
|
0x00000000, # 0x14
|
|
0x00000000, # 0x18
|
|
0xdeadc0de, # 0x1c
|
|
],
|
|
),
|
|
"32bit_sequential": dict(
|
|
pattern=[
|
|
# address, data
|
|
(0x02, 0xabadcafe),
|
|
(0x03, 0xbaadf00d),
|
|
(0x04, 0xcafefeed),
|
|
(0x05, 0xdeadc0de),
|
|
],
|
|
expected=[
|
|
# data, address
|
|
0x00000000, # 0x00
|
|
0x00000000, # 0x04
|
|
0xabadcafe, # 0x08
|
|
0xbaadf00d, # 0x0c
|
|
0xcafefeed, # 0x10
|
|
0xdeadc0de, # 0x14
|
|
0x00000000, # 0x18
|
|
0x00000000, # 0x1c
|
|
],
|
|
),
|
|
"32bit_long_sequential": dict(pattern=[], expected=[0] * 64),
|
|
}
|
|
|
|
# 32bit_long_sequential
|
|
for i in range(32):
|
|
data["32bit_long_sequential"]["pattern"].append((i, 64 + i))
|
|
data["32bit_long_sequential"]["expected"][i] = 64 + i
|
|
|
|
def half_width(data, from_width):
|
|
half_mask = 2**(from_width//2) - 1
|
|
chunks = [(val & half_mask, (val >> from_width//2) & half_mask) for val in data]
|
|
return list(itertools.chain.from_iterable(chunks))
|
|
|
|
# down conversion
|
|
data["64bit_to_16bit"] = dict(
|
|
pattern = data["64bit_to_32bit"]["pattern"].copy(),
|
|
expected = half_width(data["64bit_to_32bit"]["expected"], from_width=32),
|
|
)
|
|
data["64bit_to_8bit"] = dict(
|
|
pattern = data["64bit_to_16bit"]["pattern"].copy(),
|
|
expected = half_width(data["64bit_to_16bit"]["expected"], from_width=16),
|
|
)
|
|
|
|
# up conversion
|
|
data["8bit_to_16bit"] = dict(
|
|
pattern = data["8bit_to_32bit"]["pattern"].copy(),
|
|
expected = half_width(data["8bit_to_32bit"]["expected"], from_width=32),
|
|
)
|
|
data["32bit_to_128bit"] = dict(
|
|
pattern = data["32bit_to_256bit"]["pattern"].copy(),
|
|
expected = half_width(data["32bit_to_256bit"]["expected"], from_width=256),
|
|
)
|
|
data["32bit_to_64bit"] = dict(
|
|
pattern = data["32bit_to_128bit"]["pattern"].copy(),
|
|
expected = half_width(data["32bit_to_128bit"]["expected"], from_width=128),
|
|
)
|
|
data["8bit_to_128bit"] = dict(
|
|
pattern = data["8bit_to_256bit"]["pattern"].copy(),
|
|
expected = half_width(data["8bit_to_256bit"]["expected"], from_width=256),
|
|
)
|
|
|
|
return data
|