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litedram/test
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Maciej Dudek c54fc4af82 Fix UpConverter write path not working as intended 
LiteDRAM controler does not check if wdata stream has valid signal set,
it assumes that wdata has valid data when cmd is send.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 		2022-06-27 17:49:31 +02:00
..
primitives test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies. 2020-10-02 12:30:19 +02:00
reference Update test/reference/*_init.h 2022-03-30 13:42:47 +02:00
spd_data test/spd_data: add missing files to tracking 2020-06-02 15:19:53 +02:00
summary test: fix wrong sorting in benchmarks summary 2020-02-20 09:20:38 +01:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
access_pattern.csv test: add new benchmark configuratiosns to example configuration file 2020-02-05 18:58:49 +01:00
benchmark.py test/benchmark: Switch from soc_sdram (deprecated) to soc_core. 2022-01-07 18:37:13 +01:00
benchmarks.yml test: update benchmark configuration generator 2020-02-12 15:42:50 +01:00
common.py litedram/frontend/adapter.py rewrite up converter to optimize for bandwidth 2022-06-27 17:49:31 +02:00
gen_access_pattern.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
gen_config.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
phy_common.py phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
run_benchmarks.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_adaptation.py test: check converters at higher data width ratios 2021-09-01 14:59:05 +02:00
test_adapter.py litedram/frontend/adapter.py rewrite up converter to optimize for bandwidth 2022-06-27 17:49:31 +02:00
test_axi.py frontend/AXI: Add optional Read-Modify-Write mode for cases where w.strb is not available on the DRAM side (ex when ECC is enabled). 2022-02-28 18:45:46 +01:00
test_bandwidth.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_bankmachine.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_bist.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_command_chooser.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_crossbar.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_dfi.py phy/utils: DFI rate converter for creating PHY wrappers at slower clocks 2021-08-04 12:30:56 +02:00
test_dma.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_ecc.py test/test_ecc: Update. 2021-06-08 15:07:39 +02:00
test_examples.py litedram_gen: Add initial SDRAM support (with ULX3S example). 2021-07-02 09:01:31 +02:00
test_fifo.py frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width. 2021-10-06 18:05:48 +02:00
test_init.py test/test_init: Update. 2022-05-10 10:38:55 +02:00
test_lpddr4.py phy: move regex pattern for parsing SimLogger logs to SimLogger class 2021-10-26 12:22:30 +02:00
test_lpddr5.py lpddr5: tests: add additional initial tCK delay for bitslip 2021-10-26 12:22:30 +02:00
test_modules.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_multiplexer.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_phy_utils.py test/phy_common: simplify calls to run_simulation 2021-06-22 11:41:44 +02:00
test_refresh.py test/test_refresh: Update. 2021-11-01 15:33:21 +01:00
test_sim_utils.py phy/sim_utils: support low wait times (0/1) in PulseTiming 2021-10-26 12:22:30 +02:00
test_steerer.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_timing.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_wishbone.py Fix UpConverter write path not working as intended 2022-06-27 17:49:31 +02:00