72 lines
1.4 KiB
Verilog
72 lines
1.4 KiB
Verilog
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
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`ifndef GLBL
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`define GLBL
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`timescale 1 ps / 1 ps
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module glbl ();
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parameter ROC_WIDTH = 100000;
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parameter TOC_WIDTH = 0;
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//-------- STARTUP Globals --------------
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wire GSR;
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wire GTS;
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wire GWE;
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wire PRLD;
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tri1 p_up_tmp;
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tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
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wire PROGB_GLBL;
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wire CCLKO_GLBL;
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wire FCSBO_GLBL;
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wire [3:0] DO_GLBL;
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wire [3:0] DI_GLBL;
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reg GSR_int;
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reg GTS_int;
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reg PRLD_int;
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//-------- JTAG Globals --------------
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wire JTAG_TDO_GLBL;
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wire JTAG_TCK_GLBL;
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wire JTAG_TDI_GLBL;
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wire JTAG_TMS_GLBL;
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wire JTAG_TRST_GLBL;
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reg JTAG_CAPTURE_GLBL;
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reg JTAG_RESET_GLBL;
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reg JTAG_SHIFT_GLBL;
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reg JTAG_UPDATE_GLBL;
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reg JTAG_RUNTEST_GLBL;
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reg JTAG_SEL1_GLBL = 0;
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reg JTAG_SEL2_GLBL = 0 ;
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reg JTAG_SEL3_GLBL = 0;
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reg JTAG_SEL4_GLBL = 0;
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reg JTAG_USER_TDO1_GLBL = 1'bz;
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reg JTAG_USER_TDO2_GLBL = 1'bz;
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reg JTAG_USER_TDO3_GLBL = 1'bz;
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reg JTAG_USER_TDO4_GLBL = 1'bz;
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assign (weak1, weak0) GSR = GSR_int;
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assign (weak1, weak0) GTS = GTS_int;
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assign (weak1, weak0) PRLD = PRLD_int;
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initial begin
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GSR_int = 1'b1;
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PRLD_int = 1'b1;
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#(ROC_WIDTH)
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GSR_int = 1'b0;
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PRLD_int = 1'b0;
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end
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initial begin
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GTS_int = 1'b1;
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#(TOC_WIDTH)
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GTS_int = 1'b0;
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end
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endmodule
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`endif
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