litedram/examples
Florent Kermarrec bc6a3f220a examples/sim/sim/py: remove apb interface 2018-11-17 09:30:58 +01:00
..
sim examples/sim/sim/py: remove apb interface 2018-11-17 09:30:58 +01:00
arty_config.py modules: add DDR3-800 timings for MT41J128M16 and use it on arty example 2018-10-01 11:59:54 +02:00
genesys2_config.py examples/litedram_gen: add sdram_module_speedgrade parameter 2018-10-01 11:48:15 +02:00
litedram_gen.py examples/litedram_gen: cleanup pins definition 2018-10-15 09:38:34 +02:00