Jędrzej Boczar d20e8c763b phy: move simulation related utilities to sim_utils.py		2021-08-04 10:20:45 +02:00
..
core	Merge pull request #238 from antmicro/jboc/refresh-all-banks	2021-03-31 08:50:25 +02:00
frontend	frontend/ecc: Add optional Write errors detection (checking granularity).	2021-06-09 09:27:58 +02:00
phy	phy: move simulation related utilities to sim_utils.py	2021-08-04 10:20:45 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	lpddr4: add missing copyright comments	2021-04-01 10:07:02 +02:00
dfii.py	add SPDX License identifier to header and specify file is part of LiteDRAM.	2020-08-23 15:52:08 +02:00
gen.py	litedram_gen: Remove device limitation on GENSDRPHY/ECP5DDRPHY.	2021-07-02 09:15:42 +02:00
init.py	fix gcc warning: function used but not defined	2021-05-26 10:35:28 -04:00
modules.py	Merge pull request #236 from jersey99/master	2021-04-01 19:00:51 +02:00