litedram/litedram
Florent Kermarrec da408a3982 gen: fix default csr_port_align value 2019-09-23 09:05:54 +02:00
..
core core/refresher: improve naming/parameters of refresh postponing 2019-09-11 08:38:22 +02:00
frontend frontend/wishbone: add data_width assertions 2019-09-18 21:12:23 +02:00
phy phys: improve presentation (add separators, better indent) 2019-09-11 09:50:46 +02:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common 2019-09-11 08:00:54 +02:00
dfii.py add CONTRIBUTORS file and add copyright header to all files. 2019-06-23 23:59:10 +02:00
gen.py gen: fix default csr_port_align value 2019-09-23 09:05:54 +02:00
init.py init: split by memtype 2019-09-09 12:10:48 +02:00
modules.py add ZQ periodic short calibration support (default to 1s) 2019-09-09 15:07:38 +02:00