This website requires JavaScript.
Explore
Help
Sign In
Hardware
/
litedram
mirror of
https://github.com/enjoy-digital/litedram.git
Watch
1
Star
0
Fork
You've already forked litedram
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
e5f4f828ad
litedram
/
litedram
History
Florent Kermarrec
e5f4f828ad
phy/s7ddrphy: fix dynamic rd/wrphase and dq/dqs_oe_delay for nphases=2.
2020-10-07 18:54:43 +02:00
..
core
phy/core: move rd/wrcmdphase and computation to Multiplexer.
2020-10-01 11:26:04 +02:00
frontend
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
phy
phy/s7ddrphy: fix dynamic rd/wrphase and dq/dqs_oe_delay for nphases=2.
2020-10-07 18:54:43 +02:00
__init__.py
…
common.py
common/DQSPattern: add transmission order, minor simplification on USDDRPHY.
2020-10-02 12:26:57 +02:00
dfii.py
…
gen.py
…
init.py
litedram/init/get_sdram_phy_c_header: add CL/CWL defines.
2020-09-30 19:19:31 +02:00
modules.py
modules: remove unnecessary memtypes.
2020-09-01 13:43:09 +02:00