Florent Kermarrec 85e4c995d8 litedram/gen: .init renaming no longer required with https://github.com/enjoy-digital/litex/pull/1293.		2022-05-09 18:02:57 +02:00
..
core	core/refresher: Add assert on clk_freq/tREFI ratio.	2021-11-01 14:58:41 +01:00
frontend	frontend/axi/rmw: Fix simulation mismatch between unit-test/verilator.	2022-04-11 17:49:19 +02:00
phy	phy/usddrphy/Clk: Connect cdly_value only on first clk pad.	2022-05-02 17:34:52 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	Allow for variable DQ/DQS ratio	2022-03-30 13:42:47 +02:00
dfii.py	dfii: Improve hardware/software control comments.	2022-03-28 14:27:41 +02:00
gen.py	litedram/gen: .init renaming no longer required with https://github.com/enjoy-digital/litex/pull/1293.	2022-05-09 18:02:57 +02:00
init.py	Allow for variable DQ/DQS ratio	2022-03-30 13:42:47 +02:00
modules.py	Added AS4C4M16 residing on Arduino MKR Vidor 4000	2022-03-21 18:56:57 -07:00