litedram/litedram
2018-01-31 09:32:21 +01:00
..
core global: reset_less optimizations 2017-07-01 11:18:05 +02:00
frontend frontend/dma: add description of fifo_buffered parameter 2018-01-31 09:32:21 +01:00
phy Fix all remaining indentation issues in python code 2018-01-13 13:22:08 +11:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py global: reset_less optimizations 2017-07-01 11:18:05 +02:00
dfii.py only use positive logic in the controller(cas/ras/we) and use Record/stream.Endpoint for command requests 2016-05-02 12:18:56 +02:00
modules.py modules: add MT46H32M32 2017-07-25 10:34:03 +02:00