Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
litedram/test
History
Jędrzej Boczar ee9c2b4cf7 lpddr4: implement ZQC through MPC and include it in init sequence 
We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
 		2021-03-25 15:19:16 +01:00
..
primitives test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies. 2020-10-02 12:30:19 +02:00
reference test/reference: update. 2021-02-16 18:35:53 +01:00
spd_data test/spd_data: add missing files to tracking 2020-06-02 15:19:53 +02:00
summary test: fix wrong sorting in benchmarks summary 2020-02-20 09:20:38 +01:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
access_pattern.csv test: add new benchmark configuratiosns to example configuration file 2020-02-05 18:58:49 +01:00
benchmark.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
benchmarks.yml test: update benchmark configuration generator 2020-02-12 15:42:50 +01:00
common.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
gen_access_pattern.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
gen_config.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
run_benchmarks.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_adaptation.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_adapter.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_axi.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_bandwidth.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_bankmachine.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_bist.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_command_chooser.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_crossbar.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_dma.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_ecc.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_examples.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_fifo.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_init.py test: improve error messages when comparing files in test_init.py 2021-01-28 17:44:13 +01:00
test_lpddr4.py lpddr4: implement ZQC through MPC and include it in init sequence 2021-03-25 15:19:16 +01:00
test_modules.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_multiplexer.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_refresh.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_steerer.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_timing.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00
test_wishbone.py add SPDX License identifier to header and specify file is part of LiteDRAM. 2020-08-23 15:52:08 +02:00