Benjamin Herrenschmidt efad6b3ca5 gen: Add option to specify CSR base for standalone cores ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2020-05-12 21:55:05 +10:00
..
core	Merge pull request #179 from antmicro/jboc/docs	2020-04-10 19:58:45 +02:00
frontend	frontend/bist: simplify and fix CDC using AsyncFIFO.	2020-04-14 18:13:33 +02:00
phy	phy: extend Bitslip capability to 2 sys_clk cycles.	2020-05-08 13:12:17 +02:00
__init__.py	update code, start bankmachine refactoring and remove old code (will be rewritten)	2015-09-15 10:22:39 +02:00
common.py	common/BitSlip: add cycles parameter to extend bitstlip to multiple system clock cycles.	2020-05-08 13:09:54 +02:00
dfii.py	dfii: use reset_less on datapath/configuration CSRStorages.	2020-04-06 13:17:47 +02:00
gen.py	gen: Add option to specify CSR base for standalone cores	2020-05-12 21:55:05 +10:00
init.py	phy: extend Bitslip capability to 2 sys_clk cycles.	2020-05-08 13:12:17 +02:00
modules.py	modules: add MT41J512M16/MT41K512M16.	2020-05-09 16:37:24 +02:00