litedram/litedram
2018-10-19 18:26:45 +02:00
..
core core/bankmachine: typo 2018-10-19 18:20:12 +02:00
frontend core/frontend: move crossbar to core 2018-10-19 15:07:39 +02:00
phy phy/gensdrphy: cleanup/simplify pass 2018-10-19 18:26:45 +02:00
__init__.py update code, start bankmachine refactoring and remove old code (will be rewritten) 2015-09-15 10:22:39 +02:00
common.py core: change cba_shift parameter to more explicit address_mapping parameter 2018-10-19 17:38:04 +02:00
dfii.py multirank: one cs_n/cke/odt/clk per rank 2018-09-09 14:32:15 +02:00
modules.py modules: update K4B2G1646F and use timings from datasheet 2018-10-15 08:51:08 +02:00
sdram_init.py sdram_init: min value for wr is 5 2018-09-05 23:40:04 +02:00