2015-11-13 09:11:57 -05:00
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from litex.gen import *
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2015-09-07 07:28:02 -04:00
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2015-11-13 09:11:57 -05:00
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from litex.soc.interconnect import wishbone
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2015-11-13 18:42:33 -05:00
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from litex.soc.interconnect.stream_sim import *
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2015-11-13 09:11:57 -05:00
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2015-09-08 03:50:45 -04:00
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from liteeth.common import *
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from liteeth.core import LiteEthIPCore
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2015-09-07 07:28:02 -04:00
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2015-09-12 14:53:14 -04:00
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from test.model.dumps import *
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from test.model.mac import *
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from test.model.ip import *
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from test.model.icmp import *
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from test.model import phy, mac, arp, ip, icmp
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2015-09-07 07:28:02 -04:00
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ip_address = 0x12345678
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mac_address = 0x12345678abcd
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class TB(Module):
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def __init__(self):
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self.submodules.phy_model = phy.PHY(8, debug=True)
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self.submodules.mac_model = mac.MAC(self.phy_model, debug=True, loopback=False)
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self.submodules.arp_model = arp.ARP(self.mac_model, mac_address, ip_address, debug=True)
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self.submodules.ip_model = ip.IP(self.mac_model, mac_address, ip_address, debug=True, loopback=False)
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self.submodules.icmp_model = icmp.ICMP(self.ip_model, ip_address, debug=True)
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self.submodules.ip = LiteEthIPCore(self.phy_model, mac_address, ip_address, 100000)
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2016-03-21 14:30:47 -04:00
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def main_generator(dut):
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packet = MACPacket(ping_request)
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packet.decode_remove_header()
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packet = IPPacket(packet)
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packet.decode()
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packet = ICMPPacket(packet)
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packet.decode()
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dut.icmp_model.send(packet)
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2015-11-13 08:47:57 -05:00
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2016-03-21 14:30:47 -04:00
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for i in range(256):
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yield
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2015-09-07 07:28:02 -04:00
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2016-03-21 14:30:47 -04:00
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# XXX: find a way to exit properly
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import sys
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sys.exit()
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2015-09-07 07:28:02 -04:00
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if __name__ == "__main__":
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2016-03-21 14:30:47 -04:00
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tb = TB()
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generators = {
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"sys" : [main_generator(tb)],
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"eth_tx": [tb.phy_model.phy_sink.generator(),
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tb.phy_model.generator()],
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"eth_rx": tb.phy_model.phy_source.generator()
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}
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clocks = {"sys": 10,
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"eth_rx": 10,
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"eth_tx": 10}
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run_simulation(tb, generators, clocks, vcd_name="sim.vcd")
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