34 lines
1.1 KiB
Markdown
34 lines
1.1 KiB
Markdown
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## Purpose
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Example of UDP loopback with LiteETH IP/UDP hardware stack. The FPGA will echo back any UDP packet it
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receives on the specified port (default=8000) to the sender.
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You can also found a detailed tutorial [here](https://yehowshuaimmanuel.com/fpga/migen/ethernet_ecp5/).
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## Usage
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#!bash
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./versa_ecp5.py
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./versa_ecp5.py load
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The IP address assigned to the FPGA in this example is ``192.168.1.50`` and the Host is expected to
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be configured with ``192.168.1.100``. Since ``192.168.1.XXX`` is a common address in home networks, a
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collisiton is quite possible and in this case, you will need to re-configure the FPGA and the python
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scripts accordingly.
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Once you are able to ping the FPGA board from your computer, you can run the sender and listener scripts
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and should see the date/time UDP packets emitted by the sender looped back to the the listener:
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#!bash
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$python3 listener.py &
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$python3 sender.py
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2019-11-20 08:31:00
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2019-11-20 08:31:01
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2019-11-20 08:31:01
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2019-11-20 08:31:02
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2019-11-20 08:31:02
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2019-11-20 08:31:03
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2019-11-20 08:31:03
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2019-11-20 08:31:04
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2019-11-20 08:31:04
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[...]
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