103 lines
4.0 KiB
Python
103 lines
4.0 KiB
Python
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#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2018 David Shah <dave@ds0.me>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse
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import sys
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from migen import *
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from litex_boards.platforms import ulx3s
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from litex_boards.targets.ulx3s import _CRG
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.gpio import GPIOOut
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from litedram import modules as litedram_modules
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litex.build.generic_platform import *
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from liteeth.phy import LiteEthPHYETHERNET
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# IOs ----------------------------------------------------------------------------------------------
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_eth_io = [
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# Direct connect 10BASE-T, full-duplex Ethernet
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("eth", 0,
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Subsignal("td_p", Pins("A2")), # J1 GP9 - Green/White
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Subsignal("td_n", Pins("B1")), # J1 GN9 - Green
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Subsignal("rd_p", Pins("C4"), IOStandard("LVDS"), Misc("DIFFRESISTOR=100")), # J1 GP10 - Orange/White
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Subsignal("rd_n", Pins("B4")), # J1 GN10 - Orange
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IOStandard("LVCMOS33"),
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),
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]
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# Bench SoC ----------------------------------------------------------------------------------------
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class BenchSoC(SoCCore):
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def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
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sys_clk_freq=int(40e6), **kwargs):
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platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
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platform.add_extension(_eth_io)
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# SoCCore ----------------------------------------------------------------------------------
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SoCMini.__init__(self, platform, sys_clk_freq,
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ident = "LiteEth bench on ULX3S",
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ident_version = True,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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# Etherbone --------------------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYETHERNET(
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pads = self.platform.request("eth"),
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refclk_cd = "sys",
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with_hw_init_reset = False)
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self.add_csr("ethphy")
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self.add_etherbone(phy=self.ethphy, buffer_depth=255)
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
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parser.add_argument("--device", default="LFE5U-45F", help="FPGA device: LFE5U-12F, LFE5U-25F, LFE5U-45F (default) or LFE5U-85F")
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parser.add_argument("--revision", default="2.0", help="Board revision: 2.0 (default) or 1.7")
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parser.add_argument("--sys-clk-freq", default=40e6, help="System clock frequency (default: 50MHz)")
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builder_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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soc = BenchSoC(
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device = args.device,
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revision = args.revision,
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toolchain = args.toolchain,
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sys_clk_freq = int(float(args.sys_clk_freq)))
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
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builder.build(**builder_kargs, run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + (".svf" if args.toolchain == "trellis" else ".bit")))
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if __name__ == "__main__":
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main()
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