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phy/rmii: adapt to new syntax and fixes

This commit is contained in:
Florent Kermarrec 2015-11-19 15:42:51 +01:00
parent f1725d5fd1
commit 09dad1b520
2 changed files with 9 additions and 11 deletions
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2
liteeth/core/mac/core/__init__.py
View File

@ -24,7 +24,7 @@ class LiteEthMACCore(Module, AutoCSR):
rx_pipeline += [rx_gap_checker] rx_pipeline += [rx_gap_checker]
# Preamble / CRC # Preamble / CRC
if isinstance(phy, LiteEthPHYSim): if isinstance(phy, LiteEthPHYModel):
# In simulation, avoid CRC/Preamble to enable direct connection # In simulation, avoid CRC/Preamble to enable direct connection
# to the Ethernet tap. # to the Ethernet tap.
self._preamble_crc = CSRStatus(reset=1) self._preamble_crc = CSRStatus(reset=1)

18
liteeth/phy/rmii.py
View File

@ -6,15 +6,13 @@ def converter_description(dw):
return EndpointDescription(payload_layout, packetized=True) return EndpointDescription(payload_layout, packetized=True)
@DecorateModule(InsertCE) @CEInserter()
class LiteEthPHYRMIITX(Module): class LiteEthPHYRMIITX(Module):
def __init__(self, pads): def __init__(self, pads):
self.sink = sink = Sink(eth_phy_description(8)) self.sink = sink = Sink(eth_phy_description(8))
# # # # # #
if hasattr(pads, "tx_er"):
self.sync += pads.tx_er.eq(0)
converter = Converter(converter_description(8), converter = Converter(converter_description(8),
converter_description(2)) converter_description(2))
self.submodules += converter self.submodules += converter
@ -30,7 +28,7 @@ class LiteEthPHYRMIITX(Module):
] ]
@DecorateModule(InsertCE) @CEInserter()
class LiteEthPHYRMIIRX(Module): class LiteEthPHYRMIIRX(Module):
def __init__(self, pads): def __init__(self, pads):
self.source = source = Source(eth_phy_description(8)) self.source = source = Source(eth_phy_description(8))
@ -44,7 +42,7 @@ class LiteEthPHYRMIIRX(Module):
converter = Converter(converter_description(2), converter = Converter(converter_description(2),
converter_description(8)) converter_description(8))
converter = InsertReset(converter) converter = ResetInserter()(converter)
self.submodules += converter self.submodules += converter
self.sync += [ self.sync += [
@ -71,13 +69,13 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
# # # # # #
# assumming 100MHz clock provided externally # assumming 100MHz clock provided externally
self.sync.cd_eth += self.ref_clk.eq(~self.ref_clk) self.sync.eth += self.ref_clk.eq(~self.ref_clk)
self.comb += clock_pads.ref_clk.eq(self.ref_clk) self.comb += clock_pads.ref_clk.eq(self.ref_clk)
self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += self.cd_eth_rx.clk.eq(self.cd_eth.clk) self.comb += self.cd_eth_rx.clk.eq(ClockSignal("eth"))
self.comb += self.cd_eth_tx.clk.eq(self.cd_eth.clk) self.comb += self.cd_eth_tx.clk.eq(ClockSignal("eth"))
if with_hw_init_reset: if with_hw_init_reset:
reset = Signal() reset = Signal()
@ -101,8 +99,8 @@ class LiteEthPHYRMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8 self.dw = 8
self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset) self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYRMIITX(pads), "eth_tx") self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIITX(pads))
self.submodules.rx = RenameClockDomains(LiteEthPHYRMIIRX(pads), "eth_rx") self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRMIIRX(pads))
self.comb += [ self.comb += [
self.tx.ce.eq(self.crg.ref_clk == 1), self.tx.ce.eq(self.crg.ref_clk == 1),
self.rx.ce.eq(self.crg.ref_clk == 1) self.rx.ce.eq(self.crg.ref_clk == 1)