Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

A few minor changes that help RGMII phy related debugging. {s6, s7, us}rgmii.py Make dw a class variable instead

This commit is contained in:
Vamsi K Vytla 2020-01-17 09:23:03 -08:00
parent 17e228d4b0
commit 0a922bb2ad
4 changed files with 9 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
liteeth/core/ip.py
View File

@ -208,7 +208,7 @@ class LiteEthIPRX(Module):
NextState("CHECK") NextState("CHECK")
) )
) )
valid = Signal(reset_less=True) self.valid = valid = Signal(reset_less=True)
self.sync += valid.eq( self.sync += valid.eq(
depacketizer.source.valid & depacketizer.source.valid &
(depacketizer.source.target_ip == ip_address) & (depacketizer.source.target_ip == ip_address) &

3
liteeth/phy/s6rgmii.py
View File

@ -246,8 +246,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
class LiteEthPHYRGMII(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR):
dw = 8
def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay))

7
liteeth/phy/s7rgmii.py
View File

@ -120,7 +120,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
tx_phase = 125e6*tx_delay*360 tx_phase = 125e6*tx_delay*360
assert tx_phase < 360 assert tx_phase < 360
pll_locked = Signal() self.pll_locked = pll_locked = Signal()
pll_fb = Signal() pll_fb = Signal()
pll_clk_tx = Signal() pll_clk_tx = Signal()
pll_clk_tx_delayed = Signal() pll_clk_tx_delayed = Signal()
@ -153,7 +153,7 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
] ]
# Reset # Reset
reset = Signal() self.reset = reset = Signal()
if with_hw_init_reset: if with_hw_init_reset:
self.submodules.hw_reset = LiteEthPHYHWReset() self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
@ -168,8 +168,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
class LiteEthPHYRGMII(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR):
dw = 8
def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay))

3
liteeth/phy/usrgmii.py
View File

@ -214,8 +214,9 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
class LiteEthPHYRGMII(Module, AutoCSR): class LiteEthPHYRGMII(Module, AutoCSR):
dw = 8
def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9): def __init__(self, clock_pads, pads, with_hw_init_reset=True, tx_delay=2e-9, rx_delay=2e-9):
self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay) self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset, tx_delay)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads)) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads, rx_delay))