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liteeth
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Prioritise overridden interrupts and memory regions

This commit is contained in:
Xiretza 2020-02-11 17:09:36 +01:00
parent ec9bc578f2
commit 153c160670
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1 changed files with 6 additions and 6 deletions
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12
liteeth/gen.py
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@ -198,15 +198,15 @@ class PHYCore(SoCMini):
# MAC Core -----------------------------------------------------------------------------------------
class MACCore(PHYCore):
interrupt_map = {
interrupt_map = SoCCore.interrupt_map
interrupt_map.update({
"ethmac": 2,
}
interrupt_map.update(SoCCore.interrupt_map)
})
mem_map = {
mem_map = SoCCore.mem_map
mem_map.update({
"ethmac": 0x50000000
}
mem_map.update(SoCCore.mem_map)
})
def __init__(self, phy, clk_freq, endianness):
PHYCore.__init__(self, phy, clk_freq)