core/mac: remove frontend directory (too much directories) and some cleanup

liteeth/core/mac/__init__.py

@@ -1,7 +1,7 @@
 from liteeth.common import *
 from liteeth.core.mac.common import *
 from liteeth.core.mac.core import LiteEthMACCore
-from liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
+from liteeth.core.mac.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):

liteeth/core/mac/core.py

@@ -1,5 +1,5 @@
 from liteeth.common import *
-from liteeth.core.mac.core import gap, preamble, crc, padding, last_be
+from liteeth.core.mac import gap, preamble, crc, padding, last_be
 from liteeth.phy.model import LiteEthPHYModel
 
 

liteeth/core/mac/crc.py

@@ -140,7 +140,6 @@ class LiteEthMACCRCInserter(Module):
     def __init__(self, crc_class, description):
         self.sink = sink = stream.Endpoint(description)
         self.source = source = stream.Endpoint(description)
-        self.busy = Signal()
 
         # # #
 
@@ -160,7 +159,7 @@ class LiteEthMACCRCInserter(Module):
         fsm.act("COPY",
             crc.ce.eq(sink.stb & source.ack),
             crc.data.eq(sink.data),
-            sink.connect(source, leave_out=set(["eop"])),
+            sink.connect(source),
             source.eop.eq(0),
             If(sink.stb & sink.eop & source.ack,
                 NextState("INSERT"),
@@ -192,7 +191,6 @@ class LiteEthMACCRCInserter(Module):
                 source.data.eq(crc.value),
                 If(source.ack, NextState("IDLE"))
             )
-        self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
 
 
 class LiteEthMACCRC32Inserter(LiteEthMACCRCInserter):
@@ -221,7 +219,6 @@ class LiteEthMACCRCChecker(Module):
     def __init__(self, crc_class, description):
         self.sink = sink = stream.Endpoint(description)
         self.source = source = stream.Endpoint(description)
-        self.busy = Signal()
 
         # # #
 
@@ -278,7 +275,6 @@ class LiteEthMACCRCChecker(Module):
                 )
             )
         )
-        self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
 
 
 class LiteEthMACCRC32Checker(LiteEthMACCRCChecker):

liteeth/core/mac/gap.py

@@ -1,5 +1,8 @@
+import math
+
 from liteeth.common import *
 
+
 class LiteEthMACGap(Module):
     def __init__(self, dw, ack_on_gap=False):
         self.sink = sink = stream.Endpoint(eth_phy_description(dw))
@@ -7,7 +10,7 @@ class LiteEthMACGap(Module):
 
         # # #
 
-        gap = ceil(eth_interpacket_gap/(dw//8))
+        gap = math.ceil(eth_interpacket_gap/(dw//8))
         counter = Signal(max=gap)
         counter_reset = Signal()
         counter_ce = Signal()

liteeth/core/mac/padding.py

@@ -1,3 +1,5 @@
+import math
+
 from liteeth.common import *
 
 
@@ -8,7 +10,7 @@ class LiteEthMACPaddingInserter(Module):
 
         # # #
 
-        padding_limit = ceil(padding/(dw/8))-1
+        padding_limit = math.ceil(padding/(dw/8))-1
 
         counter = Signal(16, reset=1)
         counter_done = Signal()
@@ -57,7 +59,7 @@ class LiteEthMACPaddingChecker(Module):
 
         # # #
 
-        # XXX see if we should drop the packet when
+        # TODO: see if we should drop the packet when
         # payload size < minimum ethernet payload size
         self.comb += sink.connect(source)
 

liteeth/core/mac/sram.py

@@ -40,11 +40,12 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
         counter = Signal(lengthbits)
         counter_reset = Signal()
         counter_ce = Signal()
-        self.sync += If(counter_reset,
-                        counter.eq(0)
-                    ).Elif(counter_ce,
-                        counter.eq(counter + increment)
-                    )
+        self.sync += \
+            If(counter_reset,
+                counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + increment)
+            )
 
         # slot computation
         slot = Signal(slotbits)
@@ -156,11 +157,12 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
         counter = Signal(lengthbits)
         counter_reset = Signal()
         counter_ce = Signal()
-        self.sync += If(counter_reset,
-                            counter.eq(0)
-                        ).Elif(counter_ce,
-                            counter.eq(counter + 4)
-                        )
+        self.sync += \
+            If(counter_reset,
+                counter.eq(0)
+            ).Elif(counter_ce,
+                counter.eq(counter + 4)
+            )
 
 
         # fsm

liteeth/core/mac/wishbone.py

@@ -1,5 +1,5 @@
 from liteeth.common import *
-from liteeth.core.mac.frontend import sram
+from liteeth.core.mac import sram
 
 from litex.soc.interconnect import wishbone
 from litex.gen.fhdl.simplify import FullMemoryWE