liteeth/gen: update
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@ -210,13 +210,14 @@ class MACCore(PHYCore):
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PHYCore.__init__(self, phy, clk_freq)
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
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self.add_csr("ethmac")
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class _WishboneBridge(Module):
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def __init__(self, interface):
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self.wishbone = interface
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self.wishbone.data_width = 32
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bridge = _WishboneBridge(self.platform.request("wishbone"))
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self.submodules += bridge
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