Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

core/ip: Add optional input buffer on LiteEthIPTX to improve timings.

This commit is contained in:
Florent Kermarrec 2024-04-04 17:26:54 +02:00
parent 30e66a7e21
commit 211cdc26f3
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
liteeth/core/ip.py
View File

@ -94,13 +94,19 @@ class LiteEthIPV4Packetizer(Packetizer):
class LiteEthIPTX(LiteXModule): class LiteEthIPTX(LiteXModule):
def __init__(self, mac_address, ip_address, arp_table, dw=8): def __init__(self, mac_address, ip_address, arp_table, dw=8, with_buffer=False):
self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw)) self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw))
self.source = source = stream.Endpoint(eth_mac_description(dw)) self.source = source = stream.Endpoint(eth_mac_description(dw))
self.target_unreachable = Signal() self.target_unreachable = Signal()
# # # # # #
# Buffer.
if with_buffer:
self.buffer = buffer = stream.Buffer(eth_ipv4_user_description(dw))
self.comb += sink.connect(buffer.sink)
sink = buffer.source
# Checksum. # Checksum.
self.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True) self.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
self.comb += checksum.ce.eq(sink.valid) self.comb += checksum.ce.eq(sink.valid)