core: improve indent.

liteeth/core/arp.py

@@ -33,22 +33,14 @@ class LiteEthARPTX(Module):
 
         # # #
 
-        self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw)
-
         counter = Signal(max=max(arp_header.length, eth_min_len), reset_less=True)
-        counter_reset = Signal()
-        counter_ce = Signal()
-        self.sync += \
-            If(counter_reset,
-                counter.eq(0)
-            ).Elif(counter_ce,
-                counter.eq(counter + 1)
-            )
+
+        self.submodules.packetizer = packetizer = LiteEthARPPacketizer(dw)
 
         self.submodules.fsm = fsm = FSM(reset_state="IDLE")
         fsm.act("IDLE",
             sink.ready.eq(1),
-            counter_reset.eq(1),
+            NextValue(counter, 0),
             If(sink.valid,
                 sink.ready.eq(0),
                 NextState("SEND")
@@ -79,7 +71,7 @@ class LiteEthARPTX(Module):
             source.sender_mac.eq(mac_address),
             source.ethernet_type.eq(ethernet_type_arp),
             If(source.valid & source.ready,
-                counter_ce.eq(1),
+                NextValue(counter, counter + 1),
                 If(source.last,
                     sink.ready.eq(1),
                     NextState("IDLE")
@@ -102,7 +94,7 @@ class LiteEthARPRX(Module):
         self.sink   = sink   = stream.Endpoint(eth_mac_description(dw))
         self.source = source = stream.Endpoint(_arp_table_layout)
 
-        # # #
+        # # #s
 
         self.submodules.depacketizer = depacketizer = LiteEthARPDepacketizer(dw)
         self.comb += sink.connect(depacketizer.sink)

liteeth/core/ip.py

@@ -74,11 +74,8 @@ class LiteEthIPV4Checksum(Module):
         counter    = Signal(max=n_cycles+1)
         counter_ce = Signal()
         self.sync += If(counter_ce, counter.eq(counter + 1))
-
-        self.comb += [
-            counter_ce.eq(~self.done),
-            self.done.eq(counter == n_cycles)
-        ]
+        self.comb += counter_ce.eq(~self.done)
+        self.comb += self.done.eq(counter == n_cycles)
 
 # IP TX --------------------------------------------------------------------------------------------
 
@@ -99,10 +96,8 @@ class LiteEthIPTX(Module):
         # # #
 
         self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
-        self.comb += [
-            checksum.ce.eq(sink.valid),
-            checksum.reset.eq(source.valid & source.last & source.ready)
-        ]
+        self.comb += checksum.ce.eq(sink.valid)
+        self.comb += checksum.reset.eq(source.valid & source.last & source.ready)
 
         self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer(dw)
         self.comb += [

liteeth/core/udp.py

@@ -49,7 +49,8 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
             self.comb += tx_stream.connect(tx_cdc.sink)
             tx_stream = tx_cdc.source
         if dw != self.dw:
-            tx_converter = stream.StrideConverter(eth_udp_user_description(user_port.dw),
+            tx_converter = stream.StrideConverter(
+                eth_udp_user_description(user_port.dw),
                 eth_udp_user_description(self.dw))
             self.submodules += tx_converter
             self.comb += tx_stream.connect(tx_converter.sink)
@@ -59,7 +60,8 @@ class LiteEthUDPCrossbar(LiteEthCrossbar):
         # rx
         rx_stream = internal_port.source
         if dw != self.dw:
-            rx_converter = stream.StrideConverter(eth_udp_user_description(self.dw),
+            rx_converter = stream.StrideConverter(
+                eth_udp_user_description(self.dw),
                 eth_udp_user_description(user_port.dw))
             self.submodules += rx_converter
             self.comb += rx_stream.connect(rx_converter.sink)