fix imports

README

@@ -66,7 +66,7 @@ devel [AT] lists.m-labs.hk.
   git clone https://github.com/m-labs/misoc --recursive
 
 4. Build and load UDP loopback design (only for KC705 for now):
-  go to misoclib/com/liteeth/example_designs/
+  go to ./example_designs/
   run ./make.py -t udp all load-bitstream
 
 5. Test design (only for KC705 for now):
@@ -83,7 +83,7 @@ devel [AT] lists.m-labs.hk.
   run ./make.py test_etherbone
 
 [> Simulations:
-  Simulations are available in misoclib/com/liteeth/test/:
+  Simulations are available in ./test/:
     - mac_core_tb
     - mac_wishbone_tb
     - arp_tb
@@ -91,7 +91,7 @@ devel [AT] lists.m-labs.hk.
     - icmp_tb
     - udp_tb
   All ethernet layers have their own model tested against real ethernet dumps (dumps.py)
-  To run a simulation, move to misoclib/com/liteeth/test/ and run:
+  To run a simulation, move to ./test/ and run:
     make simulation_name
 
 [> Tests :

doc/source/docs/getting_started/downloads.rst

@@ -5,4 +5,4 @@ Download and install
 ====================
 Please follow Getting started section of LiteEth README_.
 
-.. _README: https://github.com/m-labs/misoc/blob/master/misoclib/com/liteeth/README
+.. _README: https://github.com/enjoy-digital/liteeth/README

example_designs/make.py

@@ -16,7 +16,9 @@ from mibuild import tools
 from mibuild.xilinx.common import *
 
 from misoclib.soc import cpuif
-from misoclib.com.liteeth.common import *
+liteeth_path = "../"
+sys.path.append(liteeth_path) # XXX
+from liteeth.common import *
 
 
 def _import(default, name):

example_designs/targets/base.py

@@ -10,9 +10,9 @@ from misoclib.tools.litescope.core.port import LiteScopeTerm
 
 from misoclib.com.uart.bridge import UARTWishboneBridge
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.core import LiteEthUDPIPCore
+from liteeth.common import *
+from liteeth.phy import LiteEthPHY
+from liteeth.core import LiteEthUDPIPCore
 
 
 class BaseSoC(SoC):

example_designs/targets/etherbone.py

@@ -2,10 +2,10 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 from targets.base import BaseSoC
-from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone
+from liteeth.frontend.etherbone import LiteEthEtherbone
 
 
 class EtherboneSoC(BaseSoC):

example_designs/targets/tty.py

@@ -2,10 +2,10 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 from targets.base import BaseSoC
-from misoclib.com.liteeth.frontend.tty import LiteEthTTY
+from liteeth.frontend.tty import LiteEthTTY
 
 
 class TTYSoC(BaseSoC):

example_designs/targets/udp.py

@@ -2,7 +2,7 @@ from misoclib.tools.litescope.common import *
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 from targets.base import BaseSoC
 

example_designs/test/make.py

@@ -23,7 +23,7 @@ if __name__ == "__main__":
         port = args.port if not args.port.isdigit() else int(args.port)
         wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
-        from misoclib.com.liteeth.software.wishbone import LiteETHWishboneBridgeDriver
+        from liteeth.software.wishbone import LiteETHWishboneBridgeDriver
         wb = LiteETHWishboneBridgeDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
     else:
         ValueError("Invalid bridge {}".format(args.bridge))

example_designs/test/test_etherbone.py

@@ -1,6 +1,6 @@
 import socket
 import time
-from misoclib.com.liteeth.test.model.etherbone import *
+from liteeth.test.model.etherbone import *
 
 SRAM_BASE = 0x02000000
 

liteeth/core/__init__.py

@@ -1,9 +1,9 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac import LiteEthMAC
-from misoclib.com.liteeth.core.arp import LiteEthARP
-from misoclib.com.liteeth.core.ip import LiteEthIP
-from misoclib.com.liteeth.core.udp import LiteEthUDP
-from misoclib.com.liteeth.core.icmp import LiteEthICMP
+from liteeth.common import *
+from liteeth.core.mac import LiteEthMAC
+from liteeth.core.arp import LiteEthARP
+from liteeth.core.ip import LiteEthIP
+from liteeth.core.udp import LiteEthUDP
+from liteeth.core.icmp import LiteEthICMP
 
 
 class LiteEthIPCore(Module, AutoCSR):

liteeth/core/arp/__init__.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 _arp_table_layout = [
         ("reply", 1),

liteeth/core/icmp/__init__.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthICMPPacketizer(Packetizer):

liteeth/core/ip/__init__.py

@@ -1,6 +1,6 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.ip.checksum import *
-from misoclib.com.liteeth.core.ip.crossbar import *
+from liteeth.common import *
+from liteeth.core.ip.checksum import *
+from liteeth.core.ip.crossbar import *
 
 
 class LiteEthIPV4Packetizer(Packetizer):

liteeth/core/ip/checksum.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthIPV4Checksum(Module):

liteeth/core/ip/crossbar.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.crossbar import LiteEthCrossbar
+from liteeth.common import *
+from liteeth.crossbar import LiteEthCrossbar
 
 
 class LiteEthIPV4MasterPort:

liteeth/core/mac/__init__.py

@@ -1,7 +1,7 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.common import *
-from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
-from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
+from liteeth.common import *
+from liteeth.core.mac.common import *
+from liteeth.core.mac.core import LiteEthMACCore
+from liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):

liteeth/core/mac/common.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.crossbar import LiteEthCrossbar
+from liteeth.common import *
+from liteeth.crossbar import LiteEthCrossbar
 
 
 class LiteEthMACDepacketizer(Depacketizer):

liteeth/core/mac/core/__init__.py

@@ -1,7 +1,7 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
-from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
-from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
+from liteeth.common import *
+from liteeth.core.mac.core import gap, preamble, crc, padding, last_be
+from liteeth.phy.sim import LiteEthPHYSim
+from liteeth.phy.mii import LiteEthPHYMII
 
 
 class LiteEthMACCore(Module, AutoCSR):

liteeth/core/mac/core/crc.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthMACCRCEngine(Module):

liteeth/core/mac/core/gap.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 class LiteEthMACGap(Module):
     def __init__(self, dw, ack_on_gap=False):

liteeth/core/mac/core/last_be.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthMACTXLastBE(Module):

liteeth/core/mac/core/padding.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthMACPaddingInserter(Module):

liteeth/core/mac/core/preamble.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthMACPreambleInserter(Module):

liteeth/core/mac/frontend/sram.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 from migen.bank.description import *
 from migen.bank.eventmanager import *

liteeth/core/mac/frontend/wishbone.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.frontend import sram
+from liteeth.common import *
+from liteeth.core.mac.frontend import sram
 
 from migen.bus import wishbone
 from migen.fhdl.simplify import FullMemoryWE

liteeth/core/udp/__init__.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.udp.crossbar import *
+from liteeth.common import *
+from liteeth.core.udp.crossbar import *
 
 
 class LiteEthUDPPacketizer(Packetizer):

liteeth/core/udp/crossbar.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.crossbar import LiteEthCrossbar
+from liteeth.common import *
+from liteeth.crossbar import LiteEthCrossbar
 
 
 class LiteEthUDPMasterPort:

liteeth/crossbar.py

@@ -1,6 +1,6 @@
 from collections import OrderedDict
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 class LiteEthCrossbar(Module):
     def __init__(self, master_port, dispatch_param):

liteeth/frontend/etherbone/__init__.py

@@ -1,8 +1,8 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.frontend.etherbone.packet import *
-from misoclib.com.liteeth.frontend.etherbone.probe import *
-from misoclib.com.liteeth.frontend.etherbone.record import *
-from misoclib.com.liteeth.frontend.etherbone.wishbone import *
+from liteeth.common import *
+from liteeth.frontend.etherbone.packet import *
+from liteeth.frontend.etherbone.probe import *
+from liteeth.frontend.etherbone.record import *
+from liteeth.frontend.etherbone.wishbone import *
 
 
 class LiteEthEtherbone(Module):

liteeth/frontend/etherbone/packet.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthEtherbonePacketPacketizer(Packetizer):

liteeth/frontend/etherbone/probe.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthEtherboneProbe(Module):

liteeth/frontend/etherbone/record.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthEtherboneRecordPacketizer(Packetizer):

liteeth/frontend/etherbone/wishbone.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 from migen.bus import wishbone
 
 

liteeth/frontend/tty.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthTTYTX(Module):

liteeth/phy/__init__.py

@@ -1,27 +1,27 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 def LiteEthPHY(clock_pads, pads, clk_freq=None, **kwargs):
     # Autodetect PHY
     if hasattr(pads, "source_stb"):
         # This is a simulation PHY
-        from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
+        from liteeth.phy.sim import LiteEthPHYSim
         return LiteEthPHYSim(pads)
     elif hasattr(clock_pads, "gtx") and flen(pads.tx_data) == 8:
         if hasattr(clock_pads, "tx"):
             # This is a 10/100/1G PHY
-            from misoclib.com.liteeth.phy.gmii_mii import LiteEthPHYGMIIMII
+            from liteeth.phy.gmii_mii import LiteEthPHYGMIIMII
             return LiteEthPHYGMIIMII(clock_pads, pads, clk_freq=clk_freq, **kwargs)
         else:
             # This is a pure 1G PHY
-            from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
+            from liteeth.phy.gmii import LiteEthPHYGMII
             return LiteEthPHYGMII(clock_pads, pads, **kwargs)
     elif hasattr(pads, "rx_ctl"):
         # This is a 10/100/1G RGMII PHY
         raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
     elif flen(pads.tx_data) == 4:
         # This is a MII PHY
-        from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
+        from liteeth.phy.mii import LiteEthPHYMII
         return LiteEthPHYMII(clock_pads, pads, **kwargs)
     else:
         raise ValueError("Unable to autodetect PHY from platform file, use direct instantiation")

liteeth/phy/gmii.py

@@ -1,6 +1,6 @@
 from migen.genlib.io import DDROutput
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthPHYGMIITX(Module):

liteeth/phy/gmii_mii.py

@@ -2,11 +2,11 @@ from migen.genlib.io import DDROutput
 from migen.flow.plumbing import Multiplexer, Demultiplexer
 from migen.genlib.cdc import PulseSynchronizer
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
-from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIICRG
-from misoclib.com.liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
-from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
+from liteeth.phy.gmii import LiteEthPHYGMIICRG
+from liteeth.phy.mii import LiteEthPHYMIITX, LiteEthPHYMIIRX
+from liteeth.phy.gmii import LiteEthPHYGMIITX, LiteEthPHYGMIIRX
 
 modes = {
     "GMII": 0,

liteeth/phy/loopback.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.generic import *
+from liteeth.common import *
+from liteeth.generic import *
 
 
 class LiteEthPHYLoopbackCRG(Module, AutoCSR):

liteeth/phy/mii.py

@@ -1,4 +1,4 @@
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 def converter_description(dw):

liteeth/phy/s6rgmii.py

@@ -4,7 +4,7 @@ from migen.genlib.io import DDROutput
 from migen.genlib.misc import WaitTimer
 from migen.genlib.fsm import FSM, NextState
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthPHYRGMIITX(Module):

liteeth/phy/sim.py

@@ -1,6 +1,6 @@
 import os
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 class LiteEthPHYSimCRG(Module, AutoCSR):

liteeth/software/wishbone.py

@@ -2,7 +2,7 @@ import socket
 
 from misoclib.tools.litescope.software.driver.reg import *
 
-from misoclib.com.liteeth.test.model.etherbone import *
+from liteeth.test.model.etherbone import *
 
 
 class LiteEthWishboneBridgeDriver:

test/arp_tb.py

@@ -3,12 +3,12 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac import LiteEthMAC
-from misoclib.com.liteeth.core.arp import LiteEthARP
+from liteeth.common import *
+from liteeth.core.mac import LiteEthMAC
+from liteeth.core.arp import LiteEthARP
 
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp
+from liteeth.test.common import *
+from liteeth.test.model import phy, mac, arp
 
 ip_address = 0x12345678
 mac_address = 0x12345678abcd

test/common.py

@@ -5,7 +5,7 @@ from migen.fhdl.std import *
 from migen.flow.actor import Sink, Source
 from migen.genlib.record import *
 
-from misoclib.com.liteeth.common import *
+from liteeth.common import *
 
 
 def print_with_prefix(s, prefix=""):

test/etherbone_tb.py

@@ -3,12 +3,12 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthUDPIPCore
-from misoclib.com.liteeth.frontend.etherbone import LiteEthEtherbone
+from liteeth.common import *
+from liteeth.core import LiteEthUDPIPCore
+from liteeth.frontend.etherbone import LiteEthEtherbone
 
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp, etherbone
+from liteeth.test.common import *
+from liteeth.test.model import phy, mac, arp, ip, udp, etherbone
 
 ip_address = 0x12345678
 mac_address = 0x12345678abcd

test/icmp_tb.py

@@ -3,15 +3,15 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthIPCore
+from liteeth.common import *
+from liteeth.core import LiteEthIPCore
 
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model.dumps import *
-from misoclib.com.liteeth.test.model.mac import *
-from misoclib.com.liteeth.test.model.ip import *
-from misoclib.com.liteeth.test.model.icmp import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip, icmp
+from liteeth.test.common import *
+from liteeth.test.model.dumps import *
+from liteeth.test.model.mac import *
+from liteeth.test.model.ip import *
+from liteeth.test.model.icmp import *
+from liteeth.test.model import phy, mac, arp, ip, icmp
 
 ip_address = 0x12345678
 mac_address = 0x12345678abcd

test/ip_tb.py

@@ -3,11 +3,11 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthIPCore
+from liteeth.common import *
+from liteeth.core import LiteEthIPCore
 
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip
+from liteeth.test.common import *
+from liteeth.test.model import phy, mac, arp, ip
 
 ip_address = 0x12345678
 mac_address = 0x12345678abcd

test/mac_core_tb.py

@@ -3,11 +3,11 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
+from liteeth.common import *
+from liteeth.core.mac.core import LiteEthMACCore
 
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac
+from liteeth.test.common import *
+from liteeth.test.model import phy, mac
 
 
 class TB(Module):

test/mac_wishbone_tb.py

@@ -3,11 +3,11 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.mac import LiteEthMAC
+from liteeth.common import *
+from liteeth.core.mac import LiteEthMAC
 
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac
+from liteeth.test.common import *
+from liteeth.test.model import phy, mac
 
 
 class WishboneMaster:

test/model/arp.py

@@ -1,9 +1,9 @@
 import math
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
+from liteeth.common import *
+from liteeth.test.common import *
 
-from misoclib.com.liteeth.test.model import mac
+from liteeth.test.model import mac
 
 
 def print_arp(s):
@@ -123,8 +123,8 @@ class ARP(Module):
         request.target_ip = ip_address
 
 if __name__ == "__main__":
-    from misoclib.com.liteeth.test.model.dumps import *
-    from misoclib.com.liteeth.test.model.mac import *
+    from liteeth.test.model.dumps import *
+    from liteeth.test.model.mac import *
     errors = 0
     # ARP request
     packet = MACPacket(arp_request)

test/model/etherbone.py

@@ -1,10 +1,10 @@
 import math
 import copy
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
+from liteeth.common import *
+from liteeth.test.common import *
 
-from misoclib.com.liteeth.test.model import udp
+from liteeth.test.model import udp
 
 
 def print_etherbone(s):

test/model/icmp.py

@@ -1,9 +1,9 @@
 import math
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
+from liteeth.common import *
+from liteeth.test.common import *
 
-from misoclib.com.liteeth.test.model import ip
+from liteeth.test.model import ip
 
 
 def print_icmp(s):
@@ -84,9 +84,9 @@ class ICMP(Module):
         pass
 
 if __name__ == "__main__":
-    from misoclib.com.liteeth.test.model.dumps import *
-    from misoclib.com.liteeth.test.model.mac import *
-    from misoclib.com.liteeth.test.model.ip import *
+    from liteeth.test.model.dumps import *
+    from liteeth.test.model.mac import *
+    from liteeth.test.model.ip import *
     errors = 0
     # ICMP packet
     packet = MACPacket(ping_request)

test/model/ip.py

@@ -1,9 +1,9 @@
 import math
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
+from liteeth.common import *
+from liteeth.test.common import *
 
-from misoclib.com.liteeth.test.model import mac
+from liteeth.test.model import mac
 
 
 def print_ip(s):
@@ -131,8 +131,8 @@ class IP(Module):
                 self.icmp_callback(packet)
 
 if __name__ == "__main__":
-    from misoclib.com.liteeth.test.model.dumps import *
-    from misoclib.com.liteeth.test.model.mac import *
+    from liteeth.test.model.dumps import *
+    from liteeth.test.model.mac import *
     errors = 0
     # UDP packet
     packet = MACPacket(udp)

test/model/mac.py

@@ -1,8 +1,8 @@
 import math
 import binascii
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
+from liteeth.common import *
+from liteeth.test.common import *
 
 
 def print_mac(s):
@@ -134,7 +134,7 @@ class MAC(Module):
                 raise ValueError  # XXX handle this properly
 
 if __name__ == "__main__":
-    from misoclib.com.liteeth.test.model.dumps import *
+    from liteeth.test.model.dumps import *
     errors = 0
     packet = MACPacket(arp_request)
     packet.decode_remove_header()

test/model/phy.py

@@ -1,5 +1,5 @@
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
+from liteeth.common import *
+from liteeth.test.common import *
 
 
 def print_phy(s):

test/model/udp.py

@@ -1,9 +1,9 @@
 import math
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.test.common import *
+from liteeth.common import *
+from liteeth.test.common import *
 
-from misoclib.com.liteeth.test.model import ip
+from liteeth.test.model import ip
 
 
 def print_udp(s):
@@ -95,9 +95,9 @@ class UDP(Module):
                 self.etherbone_callback(packet)
 
 if __name__ == "__main__":
-    from misoclib.com.liteeth.test.model.dumps import *
-    from misoclib.com.liteeth.test.model.mac import *
-    from misoclib.com.liteeth.test.model.ip import *
+    from liteeth.test.model.dumps import *
+    from liteeth.test.model.mac import *
+    from liteeth.test.model.ip import *
     errors = 0
     # UDP packet
     packet = MACPacket(udp)

test/udp_tb.py

@@ -3,11 +3,11 @@ from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
-from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core import LiteEthUDPIPCore
+from liteeth.common import *
+from liteeth.core import LiteEthUDPIPCore
 
-from misoclib.com.liteeth.test.common import *
-from misoclib.com.liteeth.test.model import phy, mac, arp, ip, udp
+from liteeth.test.common import *
+from liteeth.test.model import phy, mac, arp, ip, udp
 
 ip_address = 0x12345678
 mac_address = 0x12345678abcd