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liteeth/gen: Use hw_init_reset for rgmii 

This re-enables hw_init_reset that was disabled in
ea24ff6 ("liteeth_gen:  improve readability and add clk_freq checks.")

A chip reset is necessary using the Microchip KSZ9031RNX
PHY on an antmicro-artix-dc-scm board (possibly depending on startup
power timing)
This commit is contained in:
Matt Johnston 2022-09-06 10:52:39 +08:00
parent 6cf7759c9b
commit 355ac6ca5d
1 changed files with 1 additions and 1 deletions
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liteeth/gen.py
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@ -204,7 +204,7 @@ class PHYCore(SoCMini):
pads = platform.request("rgmii_eth"), pads = platform.request("rgmii_eth"),
tx_delay = core_config.get("phy_tx_delay", 2e-9), tx_delay = core_config.get("phy_tx_delay", 2e-9),
rx_delay = core_config.get("phy_rx_delay", 2e-9), rx_delay = core_config.get("phy_rx_delay", 2e-9),
with_hw_init_reset = False) # FIXME: required since sys_clk = eth_rx_clk. )
else: else:
raise ValueError("Unsupported PHY") raise ValueError("Unsupported PHY")
self.submodules.ethphy = ethphy self.submodules.ethphy = ethphy