core/mac/sram: fix code refactoring
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5106bcdc0c
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@ -28,7 +28,6 @@ class LiteEthMACSRAMWriter(Module, AutoCSR):
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# length computation
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# length computation
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inc = Signal(3)
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inc = Signal(3)
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inc_cases["default"] = inc.eq(4)
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if endianness == "big":
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if endianness == "big":
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self.comb += Case(sink.last_be, {
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self.comb += Case(sink.last_be, {
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0b1000 : inc.eq(1),
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0b1000 : inc.eq(1),
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@ -213,17 +212,17 @@ class LiteEthMACSRAMReader(Module, AutoCSR):
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if endianness == "big":
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if endianness == "big":
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self.comb += If(last,
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self.comb += If(last,
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Case(length_lsb, {
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Case(length_lsb, {
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0 : source.last.be.eq(0b0001),
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0 : source.last_be.eq(0b0001),
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1 : source.last.be.eq(0b1000),
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1 : source.last_be.eq(0b1000),
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2 : source.last.be.eq(0b0100),
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2 : source.last_be.eq(0b0100),
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3 : source.last_be.eq(0b0010)
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3 : source.last_be.eq(0b0010)
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}))
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}))
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else:
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else:
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self.comb += If(last,
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self.comb += If(last,
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Case(length_lsb, {
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Case(length_lsb, {
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0 : source.last.be.eq(0b1000),
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0 : source.last_be.eq(0b1000),
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1 : source.last.be.eq(0b0001),
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1 : source.last_be.eq(0b0001),
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2 : source.last.be.eq(0b0010),
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2 : source.last_be.eq(0b0010),
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3 : source.last_be.eq(0b0100)
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3 : source.last_be.eq(0b0100)
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}))
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}))
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