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README: update

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Florent Kermarrec 2015-11-13 23:51:23 +01:00
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@ -18,7 +18,7 @@ PDF : www.enjoy-digital.fr/liteeth.pdf
--------- ---------
LiteEth provides a small footprint and configurable Ethernet core. LiteEth provides a small footprint and configurable Ethernet core.
LiteEth is part of EnjoyDigital's libraries whose aims are to lower entry level of LiteEth is part of LiteX libraries whose aims are to lower entry level of
complex FPGA cores by providing simple, elegant and efficient implementations complex FPGA cores by providing simple, elegant and efficient implementations
ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller... ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
@ -28,11 +28,12 @@ adapters to use standardized AXI or Avalon-ST streaming buses.
Since Python is used to describe the HDL, the core is highly and easily Since Python is used to describe the HDL, the core is highly and easily
configurable. configurable.
LiteEth uses technologies developed in partnership with M-Labs Ltd: LiteEth is built using LiteX and uses technologies developed in partnership with
M-Labs Ltd:
- Migen enables generating HDL with Python in an efficient way. - Migen enables generating HDL with Python in an efficient way.
- MiSoC provides the basic blocks to build a powerful and small footprint SoC. - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
LiteEth can be used as MiSoC library or can be integrated with your standard LiteEth can be used as LiteX library or can be integrated with your standard
design flow by generating the verilog rtl that you will use as a standard core. design flow by generating the verilog rtl that you will use as a standard core.
[> Features [> Features
@ -67,28 +68,25 @@ devel [AT] lists.m-labs.hk.
------------------- -------------------
1. Install Python3 and your vendor's software 1. Install Python3 and your vendor's software
2. Obtain Migen and install it: 2. Obtain LiteX and install it:
git clone https://github.com/enjoy-digital/migen git clone https://github.com/enjoy-digital/litex --recursive
cd migen cd litex
python3 setup.py install python3 setup.py install
cd .. cd ..
3. Obtain MiSoC: 3. Build and load UDP loopback design (only for KC705 for now):
git clone https://github.com/enjoy-digital/misoc --recursive
4. Build and load UDP loopback design (only for KC705 for now):
go to example_designs/ go to example_designs/
run ./make.py -t udp all load-bitstream run ./make.py -t udp all load-bitstream
5. Test design (only for KC705 for now): 4. Test design (only for KC705 for now):
try to ping 192.168.0.42 try to ping 192.168.0.42
go to example_designs/test/ go to example_designs/test/
run ./make.py test_udp run ./make.py test_udp
6. Build and load Etherbone design (only for KC705 for now): 5. Build and load Etherbone design (only for KC705 for now):
python3 make.py -t etherbone all load-bitstream python3 make.py -t etherbone all load-bitstream
7. Test design (only for KC705 for now): 6. Test design (only for KC705 for now):
try to ping 192.168.0.42 try to ping 192.168.0.42
go to example_designs/test/ go to example_designs/test/
run ./make.py test_etherbone run ./make.py test_etherbone