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frontend/Etherbone: Use new LiteX's PacketFIFO.

This commit is contained in:
Florent Kermarrec 2021-07-15 18:07:15 +02:00
parent 2b237881d9
commit 43a2ea8118
1 changed files with 10 additions and 6 deletions
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16
liteeth/frontend/etherbone.py
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@ -205,9 +205,11 @@ class LiteEthEtherboneRecordReceiver(Module):
# # # # # #
# TODO: optimize ressources (no need to store parameters as datas) self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_record_description(32),
fifo = stream.SyncFIFO(eth_etherbone_record_description(32), buffer_depth, buffered=True) payload_depth = buffer_depth,
self.submodules += fifo param_depth = 1,
buffered = True
)
self.comb += sink.connect(fifo.sink) self.comb += sink.connect(fifo.sink)
base_addr = Signal(32, reset_less=True) base_addr = Signal(32, reset_less=True)
@ -279,9 +281,11 @@ class LiteEthEtherboneRecordSender(Module):
# # # # # #
# TODO: optimize ressources (no need to store parameters as datas) self.submodules.fifo = fifo = PacketFIFO(eth_etherbone_mmap_description(32),
fifo = PacketFIFO(eth_etherbone_mmap_description(32), buffer_depth, buffered=True) payload_depth = buffer_depth,
self.submodules += fifo param_depth = 1,
buffered = True
)
self.comb += sink.connect(fifo.sink) self.comb += sink.connect(fifo.sink)
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")