phy/a7_1000basex: Switch txoutclk buffer to BUFG.

2024-03-25 16:00:39 +01:00 · 2024-03-25 16:00:39 +01:00 · 4af0c77371
parent 292551a0f1
commit 4af0c77371
1 changed files with 1 additions and 1 deletions
--- a/liteeth/phy/a7_1000basex.py
+++ b/liteeth/phy/a7_1000basex.py
@ -702,7 +702,7 @@ class A7_1000BASEX(LiteXModule):

        # Get 125MHz clocks back - the GTP is outputting 62.5MHz.
        txoutclk_rebuffer = Signal()
-        self.specials += Instance("BUFH",
+        self.specials += Instance("BUFG",
            i_I = self.txoutclk,
            o_O = txoutclk_rebuffer
        )