Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/usp_gth/gty_1000basex: Set proper CPLLREFCLKSEL for refclk_from_fabric 

As per Xilinx UG578 CPLLREFCLKSEL needs to be set to 111 when using GTGREFCLK
as clock source.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang 2024-12-16 15:50:58 +00:00
parent d2b1b0e0c5
commit 50ad88cc85
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
liteeth/phy/usp_gth_1000basex.py
View File

@ -565,7 +565,7 @@ class USP_GTH_1000BASEX(LiteXModule):
i_CPLLLOCKDETCLK = 0b0,
i_CPLLLOCKEN = 0b1,
i_CPLLPD = pll_reset,
i_CPLLREFCLKSEL = 0b001,
i_CPLLREFCLKSEL = 0b111 if refclk_from_fabric else 0b001,
i_CPLLRESET = 0b0,
i_DMONFIFORESET = 0b0,
i_DMONITORCLK = 0b0,

2
liteeth/phy/usp_gty_1000basex.py
View File

@ -581,7 +581,7 @@ class USP_GTY_1000BASEX(LiteXModule):
i_CPLLLOCKDETCLK = 0b0,
i_CPLLLOCKEN = 0b1,
i_CPLLPD = pll_reset,
i_CPLLREFCLKSEL = 0b001,
i_CPLLREFCLKSEL = 0b111 if refclk_from_fabric else 0b001,
i_CPLLRESET = 0b0,
i_DMONFIFORESET = 0b0,
i_DMONITORCLK = 0b0,