phy/ecp5rgmii: remove p_DEL_MODE (not required since we specify DEL_VALUE).
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parent
06242564f7
commit
5247a2008a
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@ -32,7 +32,6 @@ class LiteEthPHYRGMIITX(Module):
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i2 = sink.valid,
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o = tx_ctl_oddrx1f),
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Instance("DELAYG",
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p_DEL_MODE = "SCLK_ALIGNED",
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p_DEL_VALUE = 0,
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i_A = tx_ctl_oddrx1f,
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o_Z = pads.tx_ctl)
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@ -45,7 +44,6 @@ class LiteEthPHYRGMIITX(Module):
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i2 = sink.data[4+i],
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o = tx_data_oddrx1f[i]),
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Instance("DELAYG",
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p_DEL_MODE = "SCLK_ALIGNED",
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p_DEL_VALUE = 0,
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i_A = tx_data_oddrx1f[i],
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o_Z = pads.tx_data[i]
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@ -89,7 +87,6 @@ class LiteEthPHYRGMIIRX(Module, AutoCSR):
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self.specials += [
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Instance("DELAYG",
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p_DEL_MODE = "SCLK_ALIGNED",
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p_DEL_VALUE = rx_delay_taps,
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i_A = pads.rx_ctl,
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o_Z = rx_ctl_delayf),
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@ -104,7 +101,6 @@ class LiteEthPHYRGMIIRX(Module, AutoCSR):
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for i in range(4):
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self.specials += [
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Instance("DELAYG",
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p_DEL_MODE = "SCLK_ALIGNED",
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p_DEL_VALUE = rx_delay_taps,
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i_A = pads.rx_data[i],
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o_Z = rx_data_delayf[i]),
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@ -164,7 +160,6 @@ class LiteEthPHYRGMIICRG(Module, AutoCSR):
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i2 = 0,
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o = eth_tx_clk_o),
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Instance("DELAYG",
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p_DEL_MODE = "SCLK_ALIGNED",
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p_DEL_VALUE = tx_delay_taps,
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i_A = eth_tx_clk_o,
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o_Z = clock_pads.tx)
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