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core/ip: use decorators on LiteEthIPV4Checksum (cleanup)

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This commit is contained in:
Florent Kermarrec 2015-10-21 23:39:27 +02:00
parent 7321e87cbb
commit 57b671692d
1 changed files with 4 additions and 10 deletions
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14
liteeth/core/ip.py
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@ -35,10 +35,10 @@ class LiteEthIPV4Crossbar(LiteEthCrossbar):
# ip checksum # ip checksum
@DecorateModule(InsertReset)
@DecorateModule(InsertCE)
class LiteEthIPV4Checksum(Module): class LiteEthIPV4Checksum(Module):
def __init__(self, words_per_clock_cycle=1, skip_checksum=False): def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog
self.header = Signal(ipv4_header.length*8) self.header = Signal(ipv4_header.length*8)
self.value = Signal(16) self.value = Signal(16)
self.done = Signal() self.done = Signal()
@ -59,12 +59,7 @@ class LiteEthIPV4Checksum(Module):
if (i%words_per_clock_cycle) != 0: if (i%words_per_clock_cycle) != 0:
self.comb += r_next_eq self.comb += r_next_eq
else: else:
self.sync += \ self.sync += If(~self.done, r_next_eq)
If(self.reset,
r_next.eq(0)
).Elif(self.ce & ~self.done,
r_next_eq
)
n_cycles += 1 n_cycles += 1
s, r = s_next, r_next s, r = s_next, r_next
self.comb += self.value.eq(~Cat(r[8:16], r[:8])) self.comb += self.value.eq(~Cat(r[8:16], r[:8]))
@ -73,8 +68,7 @@ class LiteEthIPV4Checksum(Module):
n_cycles += 1 n_cycles += 1
self.submodules.counter = counter = Counter(max=n_cycles+1) self.submodules.counter = counter = Counter(max=n_cycles+1)
self.comb += [ self.comb += [
counter.reset.eq(self.reset), counter.ce.eq(~self.done),
counter.ce.eq(self.ce & ~self.done),
self.done.eq(counter.value == n_cycles) self.done.eq(counter.value == n_cycles)
] ]