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bench: Update (remove calls to add_csr no longer required).

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This commit is contained in:
Florent Kermarrec 2021-07-02 09:34:33 +02:00
parent 435c67dbc7
commit 5ad0e10a72
4 changed files with 0 additions and 7 deletions
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2
bench/arty.py
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@ -41,7 +41,6 @@ class BenchSoC(SoCCore):
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
with_hw_init_reset = False)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM -------------------------------------------------------------------------------------
@ -52,7 +51,6 @@ class BenchSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Main ---------------------------------------------------------------------------------------------

2
bench/colorlight_5a_75b.py
View file

@ -42,7 +42,6 @@ class BenchSoC(SoCCore):
pads = self.platform.request("eth"),
tx_delay = 0e-9,
with_hw_init_reset = False)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM -------------------------------------------------------------------------------------
@ -53,7 +52,6 @@ class BenchSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Main ---------------------------------------------------------------------------------------------

2
bench/genesys2.py
View file

@ -41,7 +41,6 @@ class BenchSoC(SoCCore):
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
with_hw_init_reset = False)
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM -------------------------------------------------------------------------------------
@ -52,7 +51,6 @@ class BenchSoC(SoCCore):
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Main ---------------------------------------------------------------------------------------------

1
bench/sim.py
View file

@ -63,7 +63,6 @@ class BenchSoC(SoCCore):
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# SRAM -------------------------------------------------------------------------------------