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mac: Use FullMemoryWE on LiteEthMACWishboneInterface to allow correct block ram inteference on Intel/Altera decices.

This commit is contained in:
Florent Kermarrec 2021-03-11 11:55:50 +01:00
parent 89b197d1a0
commit 6c3af746e2
1 changed files with 1 additions and 1 deletions
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liteeth/mac/__init__.py
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@ -37,7 +37,7 @@ class LiteEthMAC(Module, AutoCSR):
self.rx_slots = CSRConstant(nrxslots) self.rx_slots = CSRConstant(nrxslots)
self.tx_slots = CSRConstant(ntxslots) self.tx_slots = CSRConstant(ntxslots)
self.slot_size = CSRConstant(2**bits_for(eth_mtu)) self.slot_size = CSRConstant(2**bits_for(eth_mtu))
self.submodules.interface = LiteEthMACWishboneInterface(32, nrxslots, ntxslots, endianness) self.submodules.interface = FullMemoryWE()(LiteEthMACWishboneInterface(32, nrxslots, ntxslots, endianness))
self.ev, self.bus = self.interface.sram.ev, self.interface.bus self.ev, self.bus = self.interface.sram.ev, self.interface.bus
self.csrs = self.interface.get_csrs() + self.core.get_csrs() self.csrs = self.interface.get_csrs() + self.core.get_csrs()
if interface == "hybrid": if interface == "hybrid":