Hardware
/
liteeth
mirror of https://github.com/enjoy-digital/liteeth.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge pull request #78 from lschuermann/dev/phy-gmii-model 

phy/gmii: add model parameter to skip clock buffers & generation
This commit is contained in:
enjoy-digital 2021-09-27 16:58:26 +02:00 committed by GitHub
parent bcb1946711 109002985a
commit 734d948665
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 42 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
liteeth/phy/gmii.py
View File

@ -47,7 +47,7 @@ class LiteEthPHYGMIIRX(Module):
class LiteEthPHYGMIICRG(Module, AutoCSR): class LiteEthPHYGMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0): def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0, model=False):
self._reset = CSRStorage() self._reset = CSRStorage()
# # # # # #
@ -55,49 +55,56 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain()
# RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk. if not model:
self.specials += Instance("BUFG", # RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk.
i_I = clock_pads.rx, self.specials += Instance("BUFG",
o_O = ClockSignal("eth_rx"), i_I = clock_pads.rx,
) o_O = ClockSignal("eth_rx"),
# TX clock: GMII: Drive clock_pads.gtx, clock_pads.tx unused.
# MII : Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx.
self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
eth_tx_clk = Signal()
self.comb += [
If(mii_mode,
eth_tx_clk.eq(clock_pads.tx)
).Else(
eth_tx_clk.eq(clock_pads.rx)
) )
]
self.specials += Instance("BUFG",
i_I = eth_tx_clk,
o_O = ClockSignal("eth_tx"),
)
# Reset # TX clock: GMII: Drive clock_pads.gtx, clock_pads.tx unused.
self.reset = reset = Signal() # MII : Use PHY clock_pads.tx as eth_tx_clk, do not drive clock_pads.gtx.
if with_hw_init_reset: self.specials += DDROutput(1, mii_mode, clock_pads.gtx, ClockSignal("eth_tx"))
self.submodules.hw_reset = LiteEthPHYHWReset() eth_tx_clk = Signal()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset) self.comb += [
If(mii_mode,
eth_tx_clk.eq(clock_pads.tx)
).Else(
eth_tx_clk.eq(clock_pads.rx)
)
]
self.specials += Instance("BUFG",
i_I = eth_tx_clk,
o_O = ClockSignal("eth_tx"),
)
# Reset
self.reset = reset = Signal()
if with_hw_init_reset:
self.submodules.hw_reset = LiteEthPHYHWReset()
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
self.comb += reset.eq(self._reset.storage)
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
else: else:
self.comb += reset.eq(self._reset.storage) self.comb += [
if hasattr(pads, "rst_n"): self.cd_eth_rx.clk.eq(ClockSignal()),
self.comb += pads.rst_n.eq(~reset) self.cd_eth_tx.clk.eq(ClockSignal()),
self.specials += [ ]
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
class LiteEthPHYGMII(Module, AutoCSR): class LiteEthPHYGMII(Module, AutoCSR):
dw = 8 dw = 8
tx_clk_freq = 125e6 tx_clk_freq = 125e6
rx_clk_freq = 125e6 rx_clk_freq = 125e6
def __init__(self, clock_pads, pads, with_hw_init_reset=True): def __init__(self, clock_pads, pads, with_hw_init_reset=True, model=False):
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset) self.model = model
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, model=model)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads)) self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads)) self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source self.sink, self.source = self.tx.sink, self.rx.source