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Merge pull request #78 from lschuermann/dev/phy-gmii-model 

phy/gmii: add model parameter to skip clock buffers & generation
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enjoy-digital 2021-09-27 16:58:26 +02:00 committed by GitHub
parent bcb1946711 109002985a
commit 734d948665
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 42 additions and 35 deletions
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13
liteeth/phy/gmii.py
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@ -47,7 +47,7 @@ class LiteEthPHYGMIIRX(Module):
class LiteEthPHYGMIICRG(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0, model=False):
self._reset = CSRStorage()
# # #
@ -55,6 +55,7 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
if not model:
# RX clock: GMII, MII Use PHY clock_pads.rx as eth_rx_clk.
self.specials += Instance("BUFG",
i_I = clock_pads.rx,
@ -90,14 +91,20 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]
else:
self.comb += [
self.cd_eth_rx.clk.eq(ClockSignal()),
self.cd_eth_tx.clk.eq(ClockSignal()),
]
class LiteEthPHYGMII(Module, AutoCSR):
dw = 8
tx_clk_freq = 125e6
rx_clk_freq = 125e6
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
def __init__(self, clock_pads, pads, with_hw_init_reset=True, model=False):
self.model = model
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset, model=model)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source