for now use our fork of migen

example_designs/make.py

@@ -7,8 +7,8 @@ import subprocess
 import struct
 import importlib
 
-from migen.fhdl import verilog
-from migen.fhdl.structure import _Fragment
+from litex.gen.fhdl import verilog
+from litex.gen.fhdl.structure import _Fragment
 
 from litex.build.tools import write_to_file
 from litex.build.xilinx.common import *

example_designs/targets/base.py

@@ -1,5 +1,5 @@
-from migen.genlib.io import CRG
-from migen.fhdl.specials import Keep
+from litex.gen.genlib.io import CRG
+from litex.gen.fhdl.specials import Keep
 
 from litex.build.xilinx.vivado import XilinxVivadoToolchain
 from litex.soc.interconnect import wishbone

liteeth/common.py

@@ -1,11 +1,11 @@
 import math
 from collections import OrderedDict
 
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-from migen.genlib.record import *
-from migen.genlib.fsm import FSM, NextState
-from migen.genlib.misc import chooser, WaitTimer
+from litex.gen import *
+from litex.gen.genlib.resetsync import AsyncResetSynchronizer
+from litex.gen.genlib.record import *
+from litex.gen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.misc import chooser, WaitTimer
 
 from litex.soc.interconnect.stream import *
 from litex.soc.interconnect.packet import *

liteeth/core/mac/frontend/wishbone.py

@@ -2,7 +2,7 @@ from liteeth.common import *
 from litex.soc.cores.liteeth_mini.mac.frontend import sram
 
 from litex.soc.interconnect import wishbone
-from migen.fhdl.simplify import FullMemoryWE
+from litex.gen.fhdl.simplify import FullMemoryWE
 
 
 class LiteEthMACWishboneInterface(Module, AutoCSR):

liteeth/phy/gmii.py

@@ -1,4 +1,4 @@
-from migen.genlib.io import DDROutput
+from litex.gen.genlib.io import DDROutput
 
 from liteeth.common import *
 

liteeth/phy/gmii_mii.py

@@ -1,5 +1,5 @@
-from migen.genlib.io import DDROutput
-from migen.genlib.cdc import PulseSynchronizer
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.cdc import PulseSynchronizer
 
 from litex.soc.interconnect.stream import Multiplexer, Demultiplexer
 

liteeth/phy/s6rgmii.py

@@ -1,8 +1,8 @@
 # RGMII PHY for Spartan-6
 
-from migen.genlib.io import DDROutput
-from migen.genlib.misc import WaitTimer
-from migen.genlib.fsm import FSM, NextState
+from litex.gen.genlib.io import DDROutput
+from litex.gen.genlib.misc import WaitTimer
+from litex.gen.genlib.fsm import FSM, NextState
 
 from liteeth.common import *
 

test/arp_tb.py

@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from litex.gen.fhdl.std import *
+from litex.gen.bus import wishbone
+from litex.gen.bus.transactions import *
+from litex.gen.sim.generic import run_simulation
 
 from liteeth.common import *
 from liteeth.core.mac import LiteEthMAC

test/common.py

@@ -1,9 +1,9 @@
 import random
 import copy
 
-from migen.fhdl.std import *
-from migen.flow.actor import Sink, Source
-from migen.genlib.record import *
+from litex.gen.fhdl.std import *
+from litex.gen.flow.actor import Sink, Source
+from litex.gen.genlib.record import *
 
 from liteeth.common import *
 

test/etherbone_tb.py

@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from litex.gen.fhdl.std import *
+from litex.gen.bus import wishbone
+from litex.gen.bus.transactions import *
+from litex.gen.sim.generic import run_simulation
 
 from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore

test/icmp_tb.py

@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from litex.gen.fhdl.std import *
+from litex.gen.bus import wishbone
+from litex.gen.bus.transactions import *
+from litex.gen.sim.generic import run_simulation
 
 from liteeth.common import *
 from liteeth.core import LiteEthIPCore

test/ip_tb.py

@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from litex.gen.fhdl.std import *
+from litex.gen.bus import wishbone
+from litex.gen.bus.transactions import *
+from litex.gen.sim.generic import run_simulation
 
 from liteeth.common import *
 from liteeth.core import LiteEthIPCore

test/mac_core_tb.py

@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from litex.gen.fhdl.std import *
+from litex.gen.bus import wishbone
+from litex.gen.bus.transactions import *
+from litex.gen.sim.generic import run_simulation
 
 from liteeth.common import *
 from liteeth.core.mac.core import LiteEthMACCore

test/mac_wishbone_tb.py

@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from litex.gen.fhdl.std import *
+from litex.gen.bus import wishbone
+from litex.gen.bus.transactions import *
+from litex.gen.sim.generic import run_simulation
 
 from liteeth.common import *
 from liteeth.core.mac import LiteEthMAC

test/udp_tb.py

@@ -1,7 +1,7 @@
-from migen.fhdl.std import *
-from migen.bus import wishbone
-from migen.bus.transactions import *
-from migen.sim.generic import run_simulation
+from litex.gen.fhdl.std import *
+from litex.gen.bus import wishbone
+from litex.gen.bus.transactions import *
+from litex.gen.sim.generic import run_simulation
 
 from liteeth.common import *
 from liteeth.core import LiteEthUDPIPCore